Vertical Fixed Pattern Noise (VFPN) is a significant issue in CMOS image sensors that employ column-parallel Analog-to-Digital Converters (ADCs). Variations in column response due to Process, Voltage, Temperature (PVT) characteristics and differential non-linearity (DNL) in ADCs contribute to VFPN, which impacts the perceptibility of noise in images. This paper proposes two primary methods for reducing VFPN: analog offset dithering to mitigate quantization noise and dynamic counter clock adjustment to compensate for DNL variation. Simulation results using sensor measurement data demonstrate that these techniques significantly reduce VFPN by randomizing quantization noise and averaging DNL-induced variations across columns. The proposed methods achieve an improvement in VFPN uniformity of over 70%, effectively enhancing image quality.

This paper describes a low power digitizer for 3D-stacked high dynamic range (HDR) CMOS image sensors (CIS). It digitizes the electrical output signals from the pixel array on the upper chip in the 3-D-stacked CIS. It consists of a single-slope analog-to-digital converters (ADC) array with a comparator array and a digital counter array. To improve the power-efficiency of the HDR image generation systems, a piecewise-linear counting technique for an intra-scene dual-conversion gain (i-DCG) methodology is proposed. To optimize the power consumption of the ADC array, a decision-feedback technique and a hybrid counter structure are utilized in the comparator array and the counter array, respectively. With the proposed digitizer architecture, the ADC consumes only 22.8$\mu \mathbf{W}/\mathbf{column}$, which is remarkably power-efficient. Implemented in a 28 nm process technology, the proof-of-concept prototype achieves a random noise (RN) of 89$\mu \mathbf{V}$, a column fixed-pattern noise (FPN) of 6.5 ppm, and an integrated nonlinearity (INL) of 2 ppm at the analog gain of 16.

This paper presents an implementation of a CMOS image sensor with a 65/28 nm Stacked CMOS process. The pixel array consists of 50 Mpixel with$1.4\ \mu\mathrm{m}$pixel pitch. The fabricated sensor uses 10-bit column-parallel single slope analog-to-digital converters (ADC). Furthermore, this work uses a new signal dependent multiple sampling technique to reduce noise of a pixel signal. The proposed image sensor achieves a temporal random noise of$1.4\ \mathrm{e}_{\text{rms}}^{-}$and a figure-of-merit of analog-to-digital converters (ADCs) achieves 0.477 e-nJ at 50 Mp 18 fps while it consumes 308 mW.

This paper describes a 108 mega pixels (Mp) CMOS image sensor (CIS) for mobile phone applications. The 0.7 $\mu$m-pitch pixel array ($12000\times 9000$) is composed of nona-cell ($3\times 3$ unit pixel structure) cluster with binning capability for maximum light absorption. In considerations of the trade-off between area occupation and frame rate, the column-parallel topology with thousands of single-slope ADCs is chosen for the digitizer. To suppress the horizontal noise (HN) source, an ADC decision-feedback technique is proposed to minimize the current consumption difference between before and after the ADC decision. Furthermore, with the decision-feedback loop, which is implemented in each of the comparators of the ADC array, analog power consumption can be also reduced. Top pixel and bottom digitizer chips were fabricated in 65 nm and 28 nm process technologies, respectively. The measurement results of the 3-D stacked prototype imager show an input-referred random noise (RN) of 1.4 $\mathrm{e}_{\mathrm{rms}}^{-}$ with an analog gain of 16 and a frame rate of 10 fps. A suppressed RN of 0.44 $\mathrm{e}_{\mathrm{rms}}^{-}$ is also achieved with a nona-binning. The column fixed-pattern noise (FPN) of the 108 MP imager is only 66 ppm. The high-resolution image sensing system with the decision-feedback technique achieves a figure-of-merit (FoM) of 0.71 e.nJ.

This paper presents a 1/1.33-inch 108Mp (megapixel) CMOS image sensor (CIS) for mobile applications. It is a 3D-stacked CIS designed with 0. 8um unit pixels having dual conversion gain (DCG). This work in which the NONACELL technology is applied proves large-pixel effect which provides improved performance in low lux condition at submicron pixels. The number of photodiodes increases due to the NONACELL technology, the full well capacity (FWC) can be increased due to the proposed DCG technology as well. In addition, in the proposed high dynamic range (HDR) structure, image can be displayed with a frame rate that is 3 times higher than traditional 3D-HDR.

This paper presents an implementation of a CMOS image sensor with a 65 nm CMOS process. The pixel array consists of 13 Mp with 1.12 μm pixel pitch. The fabricated sensor uses 10-bit column-parallel single slope analog-to-digital converters (ADC) based on a low-power readout architecture. Furthermore, a low-power built-in self-test (BIST) is proposed to avoid test over-kills. The proposed image sensor achieves a frame rate of 30–120 frames/s, a temporal random noise of 2 e−rms, a dynamic range of 65.2dB, peak integral non-linearity of 0.18 % and peak differential non-linearity of 0.26 least-significant bits. It consumes only 99.7mW at 30 frames/s.