We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and performance constraints. Our unique statistical estimation technique associates low-level, technology dependent physical and electrical parameters, with expected circuit resources and interconnect. Further correlations with switching activity yield accurate results consistent with implementations. All feasible designs are investigated using this technique and the designer may tradeoff between small size, high speed, low energy, and low power. The results for designs of two popular signal processing applications, predicted prior to synthesis, are within 10% accuracy of power estimates performed on synthesized layouts.

The shifting trends in software systems from custom-built to specification, and homogeneous to object-oriented and component-based, have necessitated the development of new approaches for their analysis and evaluation. Correspondingly, the last few years have seen a number of architecture-based techniques employing analytical methods, simulation and experimentation to characterize the behavior of such systems. Whereas most of the previously reported efforts were focussed on the evaluation of software systems using architecture-based techniques, the utility of these techniques in the design phase to evaluate a set of competing alternatives remains largely unexplored. In this paper, we develop an optimization framework founded on the architecture-based analysis techniques, and describe how the framework can be used to evaluate cost and reliability tradeoffs using a genetic algorithm. The choice of genetic algorithms as the underlying optimization technique is motivated by three facts, namely a potentially large and discontinuous search space, a usually nonlinear but monotonic relation between the cost and reliability of individual modules comprising the software, and complex software architectures giving rise to nonlinear dependencies between individual module reliabilities and the overall system reliability. We conclude the paper by illustrating the framework with several examples.

In typical hardware implementations of an arithmetic-intensive algorithm, designers must determine the word lengths of resources such as adders, multipliers, and registers. This paper presents algorithmic level theory and optimization techniques to select distinct word lengths for each computation which meet the desired accuracy and minimize the design cost for the given performance constraints. The reduction in cost is possible by avoiding unnecessary bit-level computations that do not contribute significantly to the accuracy of the final results. Thus we have introduced a new optimization variable, computation accuracy, into data-path synthesis. Our results show on an average, a 30% reduction in functional-resource area using distinct word lengths as opposed to use of a single optimized word length for the entire algorithm.

We describe a technique to estimate the energy consumed by speed-independent asynchronous (clock-less) control circuits. Because speed-independent circuits are hazard-free under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent of relative component gate delays and can be determined by simulating only a small number of input patterns proportional to the size of the circuit's Signal Transition Graph specification. Specifically, we calculate the average energy per external signal transition consumed by a circuit. This can be used to compare the energy consumption between two different circuit implementations of the same specification, to calculate average energy for a given high-level operation, and to provide average circuit power when combined with delay information.