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Chris D. Chalk

dblp:22/1523 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%
Artificial intelligence
1 paper
Deep learning architectures and training · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › analog circuit testing
analog fault detection
0.012000
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation › hardware test
fault classification
0.012000
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation
hardware verification and test
0.012000
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Machine learning › Deep learning architectures and training › feedforward neural network › shallow neural networks
probabilistic neural network
0.012000
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000

Methods — techniques the papers use, named apart from their topics

statistical classification · 0.1heteroscedastic probabilistic neural network · 0.1
YearPublicationVenuePosition
2004 Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski
J. Electron. Test.2
2000 Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification
abstract
The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques such as neural networks have been employed to automate classification. The major drawback to such techniques has been the implicit assumption that the variances of the responses of faulty circuits have been the same as each other and the same as that of the fault-free circuit. This assumption can be shown to be false. Neural networks, moreover, have proved to be slow. This paper describes a new neural network structure that clusters responses assuming different means and variances. Sophisticated statistical techniques are employed to handle situations where the variance tends to zero, such as happens with a fault that causes a response to be stuck at a supply rail. Two example circuits are used to show that this technique is significantly more accurate than other classification methods. A set of responses can be classified in the order of 1 s.
Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3