This work presents the design and validation of a Voltage Controlled Current Source (VCCS) aiming the Electrical Bio-Impedance Spectroscopy (EBS) application for Cervical Cancer Detection (CCD). Its topology relies on a modified variety of the classical Howland Current Source, whose schematic and layout were performed in the TSMC 65 nm CMOS process at a standard 1.2 V power supply. In this application, a stable sinusoidal load current must be provided with an amplitude of 10 μA to comply with international electromedical apparatus’ norms (IEC-60601-1) over a wide range of tissue impedance. Therefore, an advanced four-stage Operational Amplifier was customized to fulfill the VCCS’ requirements. The most noteworthy design outcomes were: a robust linearity, compatible with a subsequent 10-bit ADC sampling; a high output impedance, ranging from 1.59 GΩ at 100 Hz up to 159 kΩ at 1 MHz; an AC current amplitude consistently approaching 10 μA with a low DC offset of about ±1 μA for both 10 Ω and 5 kΩ loads at 1 MHz in Monte Carlo simulations; a compact area of 286x82 μm2(without pads); a power dissipation close to 3.7 mW. Consequently, the obtained specifications position the proposed VCCS as an extremely prominent block suitable to be utilized for EBS/CCD.

This article describes a design optimization method based on variable conversion applied to low-voltage (LV) CMOS analog integrated circuits. For supply voltages in the range of 0.3 to 0.6 V, traditional design variables (e.g., transistor channel width$W$and$\text {gm}/I_{D}$) are not suitable for exploring the design space, leading to impractical design solutions. We show that it is more efficient to convert the design variables into current$I_{D}$and channel length$L$, since these parameters are directly related to circuit performance for LV applications. The proposed optimization algorithm explores the design space to obtain solutions that satisfy the design constraints while analyzing the effects of process, voltage, and temperature variations (PVT). We apply the proposed method for design optimization in terms of area and power consumption of a fourth-order LV active filter preceded by a programmable gain amplifier (PGA), in 130 nm CMOS technology. A fully differential 0.6 V operational amplifier (OTA) is designed as a building block and used in the filter in a bottom-up approach. Measurements of a prototype chip validate the proposed method and resulted in a 0.784 mW, 0.066 mm2 active low-pass filter with a cutoff frequency of 2.5 MHz and attenuation that meet the requirements of the IEEE 802.15.4 technical standard for 2.4 GHz receivers.

This paper presents an improved baseline correction filter to be used in the readout front-end ASICs of gaseous detector systems in high energy physics experiments. The digital filter is based on an FIR section and used in the data pipeline running in real-time thought the input signals, allowing adequate data compression by the subsequent blocks in the processing chain. The proposed design was optimized to cope with the power and area trade-offs while hardening the block using redundancy and a novel automated design system based on artificial intelligence. This optimizer is also discussed including its logic and improvements using genetic algorithms with dynamic mutation and cross-over probabilities connected to run-time EDA tools. The designed filter was fabricated in 130 nm process, packaged and tested in the Peletron particle accelerator at the University of Sao Paulo. The device was irradiated and received a total dose of 70 krad during about one week of exposition to alpha particles without any measured failure, validating the design and solving the vulnerability with a small increase in the channel area of just 0.07%.

This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes a feedback control which reduces the common-mode voltage variations in terms of the Vds voltage of the bias transistor, and an enable/disable operation mode, which minimizes the power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to design the receiver circuit being robust to transient common-mode variations with low power consumption and high speed. The experimental DC power consumption of the transceiver is 4.6 mW at 1.25V power supply, where 1.1 mW is consumed by the receiver and 3.5 mW by the transmitter. The eye diagram proves the proper dynamic operation of the circuit until a data rate of 1.2Gbps.

A noise improved Charge Sensitive Amplifier (CSA) topology for a gaseous detector readout front-ends is presented. The proposed topology is based on the traditional cascode topology with addition of a PMOS to partially cancel the channel thermal noise and the flicker noise of the CSA input transistor. A noise improvement of about 23% was obtained without increasing power consumption. Additionally, the proposed circuit reduces the dependence of the noise on the detector capacitance. A chip with 5 front-ends channel implemented with the proposed CSA topology and a Semi-Gaussian shaper of 4thorder was designed in TSMC 130nm CMOS technology. The fabricated front-end was designed for 160ns of peaking time, sensitivity of 30mV/fC and Equivalent Noise Charge (ENC) of 428e. The measured power consumption of the CSA and of the pulse shaper were 3.3mW and 4.2mW, respectively.

The design of a dual modulus prescaler 32/33 in a 0.35μm CMOS technology is presented. In the circuit the technique called Extended True Single Phase Clock (E-TSPQ was applied. Additionally, some dedicated structures to double the data output rate were also employed. The prescaler was implemented, tested and experimental results indicated that the circuit can reach up to 4.12 GHz with 4.93 mW of power consumption at 3.6 V power supply.

A study of delay deviation in CMOS tapered buffers due to transistor mismatching is presented. Theoretical relations for the delay deviation were derived from the buffer and transistor parameters. To validate those relations, and to investigate the buffer behavior, special test structures consisting of tapered buffers configured as ring oscillators were designed in a 0.35 /spl mu/m CMOS technology. The experimental results are consistent with the proposed relations, and they show that small taper factors produce higher delay deviations. An increase of 23% in the delay standard deviation is observed when the taper factor is reduced from 6 to 2.9.

New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 /spl mu/m CMOS process is fully depicted. This prescaler, according to simulations, reaches a maximum 2.19-GHz operation rate at 5 V with a 46 mW power consumption. This new approach is also compared with a previous design (implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate) and with other recently published circuits.

We propose the definition and evaluation of an instruction set designed and tuned for multimedia applications on a digital set-top-box. The proposed instruction set had its performance evaluated in software and hardware to obtain the best cost/benefit relationship referring to performance and silicon chip area. An instruction set was obtained enhancing the performance of iDCT algorithms to achieve the needs of real time MPEG-2 video decompression and to have an extra processing power available for future more complex algorithms (e.g., MPEG-4). A RISC basic core was modeled in VHDL and the defined instruction set was added into this core. In this way, the evaluations were made through out logical simulations by implementing over FPGAs, and the results of the added instructions over the algorithm performance were evaluated using high-level synthesis tools and infield tests.

A new optimization criterion, the propagation of the minimum width pulse through the buffer is studied for design of tapered buffers draining capacitive loads. Contrary to the classic minimum delay criterion, this one produces buffers which support maximum speed signal propagation. Simulation results for a 0.8 /spl mu/m and a 0.35 /spl mu/m CMOS processes are analyzed. Semi-empirical relations are proposed to relate the minimum width pulse with the inverter gain ratio, the number of inverters, and the capacitive load. Additionally, a brief study of the delay skew of tapered buffers due to mismatching as a function of the gain ratio is done, showing that no severe degradation appears with small gain ratios. Finally, this work points out that buffers with small gain ratios should reach higher speeds, nearly 30% over the speed of buffers with gain ratio larger than a factor of 3.

The design of an 8:1 multiplexer circuit, for SDH/SONET data transmission systems, is presented. In order to achieve maximum transmission rates, new circuits, high speed input/output converters for ECL-CMOS levels and modified true single phase clocked (TSPC) cells, as well as new techniques for clock buffer optimization, were applied. The multiplexer was implemented in a 0.8 /spl mu/m CMOS process (0.7 /spl mu/m effective length) achieved 1.7 Gbit/s rate and 42.6 /spl mu/W/MHz power consumption at 5 V. These results were compared to a previous implementation (in the same process), and to other recently published works, showing superior performances.

This paper presents an output buffer which converts CMOS into ECL levels, and a brief analysis of its speed performance. The structure is designed in a 0.8 /spl mu/m CMOS process (effective length is 0.7 /spl mu/m). The circuit operation is based on current source switching. In the speed analysis we show that the speed is severely limited by the output load, and that the process, for common applications, is a secondary factor. Experimental results for the buffer operating at 1.4 Gbit/s rate are shown. The circuit is part of a 1.2 Gbit/s SDH/SONET system.