Serious games are composed of three components, namely, learning contents, learning strategies, and game elements. To emphasize the significance of game elements on learning effectiveness in serious games, this study proposed a design pattern for courses of serious games, based on serious game courses which addressed the endocrine unit for students in the seventh grade. Since the courses were first developed and put to use three years ago, the courses have been implemented and modified many times. The courses adopted in this study were the fifth version. Employing a quasi-experimental research design, an experiment of two-week courses was organized in three groups, namely the traditional instruction group, the serious game group, and the low playability game group, which used courses with less playabilities modified on the basis of serious games. A total of 234 students participated in this research. The research instruments included achievement test. The results showed that serious game courses with sufficient playabilities outperformed the low playability group and traditional group in both the achievement test, indicating that playability was an important factor influencing the effectiveness of serious game courses. Additionally, with respect to the categorical variables, gender differences had no significant influence over serious game courses. Learning background had no significant influence on the outcome of achievement test of the serious game group.

Boolean matching determines whether two given (in)completely-specified Boolean functions can be identical or complementary to each other under permutation and/or negation of their input variables. Due to its broad applications in logic synthesis and verification, it attracted much attention. Most prior efforts however were incomplete and/or restricted to certain special matching conditions. In contrast, this paper focuses on the computation kernel of Boolean matching and proposes a complete generic framework. Through conflict-driven learning and abstraction, the capacity of Boolean matching scales up due to the effective pruning of infeasible matching solutions. Experiments show encouraging results in resolving hard instances that are otherwise unsolvable.

Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negation of their inputs and outputs. Despite its importance in design rectification, technology mapping, and other logic synthesis applications, there is no much direct study on this subject due to its generality and consequent computational complexity. This paper extends our prior Boolean matching decision procedure BooM to consider multiple-output functions. Through conflict-driven learning and partial assignment reduction, Boolean matching in the most general setting can still be accomplishable even when all other techniques lose their foundation and become unapplicable. Experiments demonstrate the indispensable power of strengthened learning for practical applications.

Boolean matching is to check the equivalence of two target functions under input permutation and input/output phase assignment. This paper addresses the permutation independent (P-equivalent) Boolean matching problem. We will propose a matching algorithm seamlessly integrating Simulation and Boolean Satisfiability (S&S) techniques. Our proposed algorithm will first utilize functional properties like unateness and symmetry to reduce the searching space. In the followed simulation phase, three types of input vector generation and checking method will be used to match the inputs of two target functions. Experimental results on large benchmarking circuits demonstrate that our matching algorithm is indeed very effective and efficient to solve Boolean matching for large Boolean networks.

In this paper, we will propose an incremental learning approach to solve Boolean matching for incompletely specified functions. This approach can incrementally analyze current feasible partial mappings, detect and eliminate redundant manipulations in a proactive way. A new type of signature exploiting single variable symmetries is also given to reduce the searching space. Moreover, a SAT model of Boolean matching will be proposed to handle large Boolean functions. Through the utilization of these novel mechanisms, a drastic improvement on the performance of our Boolean matching algorithms are achieved. The experimental results demonstrate the effectiveness and efficiency of the proposed learning-based and SAT-based Boolean matching algorithms on many large benchmarking circuits.

In this paper, we present the concept of k-distance signature which is a general case of many existing signatures. By exploiting k-distance signature, we propose an Algorithm for Input Differentiation AID) which is very powerful to distinguish inputs of Boolean functions. Moreover, based on AID, we propose a heuristic method to detect gsym~of Boolean functions and a Boolean matching algorithm. The experimental results show that our methods are not only effective but also very efficient for Boolean matching and gsym~detection.

We propose a maximum crosstalk effect minimization algorithm that takes logic synthesis into consideration for PLA structures. To minimize the crosstalk effect, a technique for permuting wire is used which contains the following steps. First, product terms are partitioned into long and short sets, and then the product terms in the long and short sets are interleaved. After that, we take advantage of the crosstalk immunity of product terms in the long set to further reduce the maximum coupling capacitance of the PLA. Finally, synthesis techniques such as local and global transformations are taken into consideration to search for a better result. The experiments demonstrate that our algorithm can effectively minimize the maximum coupling capacitance of a circuit by 51% as compared with the original area-minimized PLA without crosstalk effect minimization.

A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024/spl times/2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.

In this paper, we propose a K-disjointness paradigm that can effectively search all pairs of minterms with Hamming distance K between two Boolean functions. By this paradigm, we correlate it with symmetry detection problem and propose an efficient symmetry detection algorithm for Boolean functions. Our algorithm can not only handle completely specified functions but also incompletely specified functions. Experimental results on a set of MCNC and ISCAS benchmarking circuits show that our algorithm is indeed very effective and efficient for detecting symmetries of large Boolean functions.

In this paper, we formulate symmetry detection for incompletely specified functions as an equation without using cofactor computation and equivalence checking. Based on this equation, a symmetry detection algorithm is proposed. This algorithm can simultaneously find non-equivalence and equivalence symmetries. Experimental results on a set of benchmarks show that our algorithm is indeed very effective in solving symmetry detection problem for incompletely specified functions.

We propose a maximum crosstalk minimization algorithm taking logic synthesis into consideration for PLA structure. To minimize the crosstalk, technique of permuting wire is used which includes the following steps. First, product lines are partitioned into long set and short set, and then product lines in long set and short set are interleaved. By interleaving algorithm, an upper bound on the maximum coupling capacitance of the product lines can be derived. Then, we take advantage of crosstalk immunity of product lines in long set to further reduce the maximum crosstalk effect of the PLA. Finally, synthesis techniques such as local transformation and global transformation are taken into consideration to search for a better result. The experiments demonstrate that our algorithm can effectively minimize the maximum crosstalk effect of a circuit by 48% as compared with the original area-minimized PLA without crosstalk minimization.

We present methods to generate a Binary Decision Diagram (BDD) with minimum expected path length. A BDD is a generic data structure which is widely used in several fields. One important application is the representation of Boolean functions. A BDD representation enables us to evaluate a Boolean function: Simply traverse the BDD from the root node to the terminal node and retrieve the value in the terminal node. For a BDD with minimum expected path length will be also minimized the evaluation time for the corresponding Boolean function. Three efficient algorithms for constructing BDDs with minimum expected path length are proposed.

Boolean matching is to check the equivalence of two functions under input permutation and input/output phase assignment. In this paper, we address Boolean matching problems for incompletely specified functions. We formulate the searching of input variable mapping between two target functions as a logic equation by using multiple-valued functions. Based on this equation, a Boolean matching algorithm is proposed. Delay and power dissipation can also be taken into consideration when this method is used for technology mapping. Experimental results on a set of benchmarks show that our algorithm is indeed very effective in solving the Boolean matching problem for incompletely specified functions.

Boolean matching is to check the equivalence of two functions under input permutation and input/output phase assignment. A straightforward implementation takes time complexity O(n!2/sup n/2), where n is the number of variables. Various signatures of variables were used to prune impossible permutations by many researchers. In this paper, based on communication complexity, we also propose two signatures, cofactor and equivalence signatures, which are general forms of many existing signatures. These signatures are used to develop an efficient Boolean matching algorithm which is based on checking structural equivalence of OBDD's. Experimental results on a set of benchmarks show that our algorithm is indeed very effective in solving Boolean matching problem.

Boolean matching is to check the equivalence of two functions under input permutation and input/output phase assignment.In this paper, we will address Boolean matching problem for incompletely speci ed functions.We will formulate the searching of input variable mapping between two target functions as a logic equation by using multiple-valued function.Based on this equation, a Boolean matching algorithm will be proposed.Delay and power dissipation can also be taken into consideration when this method is used for technology mapping.Experimental results on a set of benchmarks show that our algorithm is indeed very eective in solving Boolean matching problem for incompletely speci ed functions.

We address the problem of state assignment to minimize both area and power dissipation for finite state machine designs. We propose a new matching-based state-assignment algorithm which considers area and state transitions simultaneously. Experimental results on a set of benchmarks demonstrate that our approach is indeed very effective in minimizing both area and power dissipation.>

In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices.>

A set of debugging tools has been implemented for monitoring and controlling the execution sequences of Concurrent-C programs. Among these tools, REPLAY MONITOR can be employed for monitoring the synchronization events while RELAY REPRODUCER serves for reproducing the monitored synchronization events. When some processes of a concurrent program are irrelevant and time-consuming, PARTIAL REPLAY MONITOR and PARTIAL REPLAY REPRODUCER can be utilized for monitoring and reproducing synchronization events while ignoring the actual computation of those irrelevant processes in order to save debugging time.>