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Kevin W. Kark

dblp:22/2168 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.011997
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors · DAC 1997
Electronic design automation › circuit simulation
probabilistic simulation		 0.011997
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors · DAC 1997
Electronic design automation › hardware verification and test › functional verification
simulation-based verification		 0.011997
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors · DAC 1997
Processor architecture and microarchitecture › multiprocessor architecture
multiprocessor design		 0.011997
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors · DAC 1997

Methods — techniques the papers use, named apart from their topics

timing diagram generation · 0.0CAD tool support · 0.0
YearPublicationVenuePosition
1997 Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors
abstract
In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis shown how the timing diagrams for the unit network verificationare easily derived from the timing diagrams specified for theunits. The multiprocessor hardware test showed the effectivenessof the proposed verification approach.
Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile
 DAC6