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Shintaro Ushio

dblp:22/2348 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 92% Integrated circuit design · 8%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
process simulation
0.021990
A fast three-dimensional process simulator OPUS/3D with access to two-dimensional simulation results · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
A general-purpose two-dimensional process simulator-OPUS for arbitrary structures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › technology computer-aided design › process simulation
two-dimensional process simulation
0.021990
A general-purpose two-dimensional process simulator-OPUS for arbitrary structures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
A fast three-dimensional process simulator OPUS/3D with access to two-dimensional simulation results · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Integrated circuit design
semiconductor process modeling
0.011989
A general-purpose two-dimensional process simulator-OPUS for arbitrary structures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989

Methods — techniques the papers use, named apart from their topics

coordinate expansion · 0.0finite difference method · 0.0discretization · 0.0
YearPublicationVenuePosition
1990 A fast three-dimensional process simulator OPUS/3D with access to two-dimensional simulation results
abstract
A three-dimensional (3-D) process simulator, OPUS/3D, has been developed. It has access to two-dimensional (2-D) process simulation results. Impurity profiles and structural data simulated rigidly in 2-D space are expanded to 3-D space at an arbitrary stage of the simulation processes. 3-D simulation follows until the end of the process. The access to 2-D simulation results enables OPUS/3D to handle curved boundaries as seen in field oxides. OPUS/3D has three different methods for expanding 2-D results. Errors due to these expansions are discussed. OPUS/3D was applied to 3-D simulations of MOS devices at the corner edge of the active region and in the channel region near the source/drain. Computation time was drastically reduced by replacing part of the 3-D simulations by 2-D simulations. Some 3-D effects are confirmed by OPUS/3D.>
Shintaro Ushio, Kenji Nishi, Shigeki Kuroda, Kazuhiko Kai, Jun Ueda
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1989 A general-purpose two-dimensional process simulator-OPUS for arbitrary structures
abstract
A general-purpose two-dimensional process simulator OPUS (Oki Process simulator for ULSI Structures) for arbitrary structures is discussed. By separating a preprocessor from a main processor, OPUS can simulate any kind of impurity or material with up to eight impurities and ten materials. OPUS utilizes a finite-difference method for diffusion analysis without any coordinate transformation. In order to minimize errors due to discretization around the curved boundaries, OPUS has introduced two kinds of boundaries. The first is true boundaries by strings. The other is quasi-boundaries formed through simplifying but retaining the shape of true boundaries as long as possible. The quasi-boundaries and resulting dummy cells are used for discretization of the diffusion equation. General features of OPUS are first introduced with special emphasis on dummy cells. Errors caused by dummy cells are discussed. The capacity of OPUS is then demonstrated through application to a trench process and to a full MOS process with a sidewall.>
Kenji Nishi, Kouichi Sakamoto, Shigeki Kuroda, Jun Ueda, Tatsurou Miyoshi, Shintaro Ushio
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6