The advent of heterogeneous integration (HI) places new demands on EDA tooling. Building large systems requires (1) methods for chiplet disaggregation that map the system to smaller chiplets, working in conjunction with system-technology co-optimization to determine the right design decisions that optimize computation and communication, together with the choice of substrate and chiplet technologies; (2) multiphysics and multiscale analyses that incorporate thermomechanical aspects into performance analysis, ranging from fast machine-learningdriven analyses in early stages to signoff-quality multiphysics-based analysis; (3) physical design techniques for placing and routing chiplets and embedded active/passive elements on and within the substrate, including the design of thermal and power delivery solutions; and (4) underlying infrastructure required to facilitate HI-based design, including the design and characterization of chiplet libraries and the establishment of data formats and standards. This paper overviews these issues and lays out a set of EDA needs for HI designs.

Device sizing is crucial for meeting performance specifications in operational transconductance amplifiers (OTAs), and this work proposes an automated sizing framework based on a transformer model. The approach first leverages the driving-point signal flow graph (DP-SFG) to map an OTA circuit and its specifications into transformer-friendly sequential data. A specialized tokenization approach is applied to the sequential data to expedite the training of the transformer on a diverse range of OTA topologies, under multiple specifications. Under specific performance constraints, the trained transformer model is used to accurately predict DP-SFG parameters in the inference phase. The predicted DP-SFG parameters are then translated to transistor sizes using a precomputed look-up table-based approach inspired by the 9m / I d methodology. In contrast to previous conventional or machine-learning-based methods, the proposed framework achieves significant improvements in both speed and computational efficiency by reducing the need for expensive SPICE simulations within the optimization loop; instead, almost all SPICE simulations are confined to the one-time training phase. The method is validated on a variety of unseen specifications, and the sizing solution demonstrates over 90% success in meeting specifications with just one SPICE simulation for validation, and 100% success with 3–5 additional SPICE simulations.

Power delivery is a significant bottleneck in 2.5D heterogeneously integrated (HI) systems. A key part of the solution lies in the use of voltage regulators that distribute power to the chiplets with low transmission losses, thus ensuring supply levels that meet design specifications. Early HI systems have used manual approaches for placement, but as systems grow more complex and employ heterogeneous chiplets with nonuniform power distributions, the solution becomes nontrivial, and automation is essential. This paper addresses the problem of voltage regulator selection and placement for early-stage power planning in HI systems under DC estimates of chiplet loads. It demonstrates an HI technology using an active silicon interposer with embedded switched-capacitor voltage regulators (SCVRs). The problem is formulated as a 0–1 mixed integer linear program (MILP) and determines the optimal number, location, and types of SCVRs. A key part of the solution is using a macromodeling approach to control the size of the MILP. Experimental results across four test cases—covering both homogeneous and heterogeneous chiplet configurations—demonstrate that the method can efficiently find optimal solutions. The tested scenarios span a wide range of power densities, from 0.8 to 4.0W/mm2, and include total load currents ranging from 800A to 1200A. In all cases, the method achieves high accuracy (average error below 1.7%) and completes the optimization within practical runtimes, ranging from 18.8 to 46.1 minutes.

The layout area and power consumption of a charge-scaling digital-to-analog converter (DAC) is typically dominated by the capacitor array. For a binary-weighted DAC, since the number of unit capacitors in the array increases exponentially with the number of bits, minimizing the size of the unit capacitor is crucial for controlling the layout area. A split DAC uses many fewer unit capacitors than the binary-weighted DAC, but requires the use of noninteger multiples of a unit capacitance; the choice of unit capacitor remains an important consideration. Smaller capacitors can be susceptible to larger amounts of noise and process mismatch, and can also be affected by mismatch in the parasitics of routing wires that connect the capacitors in the array: the latter is particularly significant in FinFET nodes. Together, these factors can degrade critical DAC performance metrics unless the unit capacitor is sufficiently large. This work proposes a systematic approach for selecting the unit capacitance value in both binary-weighted and split capacitor arrays for charge-scaling DACs. The proposed method selects a value that optimizes the nonlinearity metrics of a DAC, accounting for multiple factors that contribute to mismatch, flicker noise, and thermal noise. Our results demonstrate that by using a systematic methodology to size the unit capacitor, it is possible to overcome shifts due to process variation and noise for 6-bit to 14-bit DACs. Particularly for higher-resolution DACs, it is seen that the minimum unit capacitor value for binary-weighted DACs is lower than for split DACs, but the former incurs much larger area costs since it contains a significantly larger number of unit capacitors.

Building upon recent advances in analog electronic design automation (EDA), this paper discusses directions for reinforcing the connection between design and EDA, in order to develop solutions that are meaningful to designers. Two aspects, both related to bridging the gap between EDA and designers, are highlighted. The first discusses the use of test structures to generate meaningful characterized data to aid design automation, specifically understanding the impact of random, correlated, and systematic variations on the design of matched structures. Results on a recent test chip that analyzes these variations and their impact on EDA design choices will be presented. The second illustrates a design testcase that applies analog EDA techniques, using the ALIGN layout engine, to design an RF MIMO receiver, and describes how this experience has helped both in advancing the state of analog EDA and in building circuits with enhanced designer productivity.

Due to the inherent error-tolerance of machine learning (ML) algorithms, many parts of the inference computation can be performed with adequate accuracy and low power under relatively low precision. Early approaches have used digital approximate computing methods to explore this space. Recent approaches using analog-based operations achieve power-efficient computation at moderate precision. This work proposes a mixed-signal optimization (MiSO) approach that optimally blends analog and digital computation for ML inference. Based on accuracy and power models, an integer linear programming formulation is used to optimize design metrics of analog/digital implementations. The efficacy of the method is demonstrated on multiple ML architectures.

In FinFET nodes, high transistor power densities in a power amplifier (PA) lead to device self-heating (SH), degrading performance. This study investigates the impact of SH in large PA FinFET arrays. An encoder-decoder network, together with a long short-term memory model, is used for rapid and accurate thermal analysis. This fast analyzer helps better explore design optimizations than conventional computationally-expensive thermal solvers. The work explores methods for mitigating thermal effects in PAs by inserting dummy transistors within the array of active FinFET devices, and shows the impact of duty cycle and frequency on PA performance.

Performance modeling is a key bottleneck for analog design automation. Although machine learning-based models have advanced the state-of-the-art, they have so far suffered from huge data preparation cost, very limited reusability, and inadequate accuracy for large circuits. We introduce ML-based macro-modeling techniques to mitigate these problems for linear analog ICs and ADC/DACs. The modeling techniques are based on macro-models, which can be assembled to evaluate circuit system performance, and more appealingly can be reused across different circuit topologies. On representative testcases, our method achieves more than$1700\times $speedup for data preparation and remarkably smaller model errors compared to recent ML approaches. It also attains$3600\times $acceleration over SPICE simulation with very small errors and reduces data preparation time for an ADC design from 40 days to 9.6 h.

The design of active array structures in analog circuits requires careful matching to minimize the impact of variations. This work presents a constructive approach for building these arrays to directly incorporate shifts due to process variations, considering systematic first-order and second order gradients; to account for systematic layout effects, including parasitic mismatch and layout-dependent effects due to stress; and to ensure that the resulting layout delivers high performance. The proposed algorithms are targeted to FinFET technologies and are validated for multiple analog blocks in a commercial 12nm FinFET process. The layouts generated by the proposed method are demonstrated to provide better matching and performance than prior methods.

Recent advances in auto-generating analog and mixed-signal (AMS) circuits use standard digital tool flows to compose AMS circuits from a combination of digital standard cells and a set of auxiliary cells (auxcells). Until now, generating auxcell layouts for each new PDK was the last manual step in the flow for auto-generating AMS components, which limited the available auxcells and reduced the optimality of the auto-generated AMS designs. To solve this, we propose AuxcellGen, a framework to auto-generate auxcell layouts and performance models. Aux-cellGen generates a parasitic-aware auxcell performance model using a neural network (NN), auto-sizes and optimizes auxcell schematics for a given design target, and auto-generates auxcell layouts. The framework is demonstrated by auto-generating tristate buffer auxcells for PLLs and sense-amplifier auxcells for SRAM across a range of user specifications that are compatible with standard cell and memory bitcell pitch.

The layout area and power consumption of a binary-weighted capacitive digital-to-analog converter (DAC) increases exponentially with the number of bits. To meet linearity targets, unit capacitors should be large enough to limit errors caused by various sources of noise and those due to mismatch. This work proposes a systematic approach for minimizing the unit capacitance value that optimizes the linearity metrics of a DAC, accounting for multiple factors that contribute to mismatch, as well as the impact of flicker and thermal noise.

Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

Analog designs consist of multiple hierarchical functional blocks. Each block can be built using one of several design topologies, where the choice of topology is based on circuit performance requirements. A major challenge in automating analog design is in the identification of these functional blocks, which enables the creation of hierarchical netlist representations. This can facilitate a variety of design automation tasks, such as circuit layout optimization, because the layout is dictated by constraints at each level, such as symmetry requirements, that depend on the topology of the hierarchical block. Traditional graph-based methods find it hard to automatically identify the large number of structural variants of each block. To overcome this limitation, this article leverages recent advances in graph neural networks (GNNs). A variety of GNN strategies is used to identify netlist elements for circuit functional blocks at higher levels of the design hierarchy, where numerous design variants are possible. At lower levels of hierarchy, where the degrees of freedom in circuit topology is limited, structures are identified using graph-based algorithms. The proposed hierarchical recognition scheme enables the identification of layout constraints, such as symmetry and matching, which enable high-quality hierarchical layouts. This method is scalable across a wide range of analog designs. An experimental evaluation shows a high degree of accuracy over a wide range of analog designs, identifying functional blocks, such as low-noise amplifiers, operational transconductance amplifiers, mixers, oscillators, and band-pass filters, in larger circuits.

Well island generation and well tap placement is an important problem in analog/mixed-signal (AMS) circuits. Well taps can only prevent latchups within a certain radius of influence within a well island, and hence must be appropriately inserted to cover all devices. However, existing automated AMS layout paradigms typically defer the insertion of well taps and creation of well islands to a post-processing step after placement. This alters the placement, resulting in increased area and wire length, as well as circuit performance degradation. Therefore, there is a strong need for a solution that generates well islands and inserts well taps during placement so the placer can account for well overheads in optimizing placement metrics. In this work, we propose a modular solution using a graph-based optimization scheme that can be used within multiple placement paradigms with minimal intrusion. We demonstrate the integration of this scheme into stochastic, analytical, and designer-driven row-based placement. The method is demonstrated in advanced FinFET technologies. Layouts generated using this scheme show better area, wire length, and performance metrics at the cost of a marginal runtime degradation when compared to the post-processing approach. Using our scheme, there is an average improvement of 3% and 4% and a maximum improvement of 23% and 11% in area and wirelength, respectively, of layouts of various classes of AMS circuits at the cost of 17% average and 29% maximum increase in total runtime.

Analog IC performance has a strong dependence on interconnect RC parasitics, which are significantly affected by wire sizes in recent technologies, where minimum-width wires have high resistance. However, performance-driven wire sizing for analog ICs has received very little research attention. In order to fill this void, we develop several techniques to facilitate an end-to-end automatic wire sizing approach. They include a circuit performance model based on customized graph neural network (GNN) and two optimization techniques: one using Bayesian optimization accelerated by the GNN model, and the other based on TensorFlow training. Experimental results show that our technique can achieve 11% circuit performance improvement or 8.7× speedup compared to a conventional Bayesian optimization method.

This paper presents an overview of common-centroid (CC) layout styles, used in analog designs to overcome the impact of systematic variations. CC layouts must be carefully engineered to minimize the impact of mismatch. Algorithms for CC layout must be aware of routing parasitics, layout-dependent effects (for active devices), and the performance impact of layout choices. The optimal CC layout further depends on factors such as the choice of the unit device and the relative impact of uncorrelated and systematic variations. The paper also examines scenarios where non-CC layouts may be preferable to CC layouts.

An analog/mixed-signal designer typically performs circuit optimization, involving intensive SPICE simulations, on a schematic netlist and then sends the optimized netlist to layout. During the layout phase, it is vital to maintain symmetry requirements to avoid performance degradation due to mismatch: these constraints are usually specified using user input or by invoking an external tool. Moreover, to achieve high performance, the layout must avoid large interconnect parasitics on critical nets. Prior works that optimize parasitics during placement work with coarse metrics such as the half-perimeter wire length, but these metrics do not appropriately emphasize performance-critical nets. The novel charge flow (CF) formulation in this work addresses both symmetry detection and parasitic optimization. By leveraging schematic-level simulations, which are available “for free” from the circuit optimization step, the approach (a) alters the objective function to emphasize the reduction of parasitics on performance-critical nets, and (b) identifies symmetric elements/element groups. The effectiveness of the CF-based approach is demonstrated on a variety of circuits within a stochastic placement engine.

The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

Analytical techniques have long been a prevailing approach to digital IC placement due to their advantage in handling large-sized problems. Recently, they have been adopted for analog IC placement, an area where prior methods were mostly based on simulated annealing. However, a comparative study between the two classes of approaches is lacking. Moreover, the effectiveness of different analytical techniques is not clear. This work attempts to shed light on both issues by studying existing methods and developing a new analytical technique. Since prior analytical methods have not addressed circuit performance, a critical concern for automated analog layout, this work also extends the new analytical placer for performance-driven placement. Experiments on various test circuits show that for a conventional performance-oblivious formulation, the proposed analytical technique achieves 55x speedup and 12% wirelength reduction compared to simulated annealing. For performance-driven placement, the proposed technique outperforms simulated annealing in terms of circuit performance, area, and runtime. Moreover, the proposed technique generally provides better solution quality than an alternative analytical technique.

Well island generation and well tap placement pose an important challenge in automated analog/mixed-signal (AMS) layout. Well taps prevent latchup within a radius of influence in a well island, and must cover all devices. Automated AMS layout flows typically perform well island generation and tap insertion as a postprocessing step after placement. However, this step is intrusive and potentially alters the placement, resulting in increased area, wire length, and performance degradation. This work develops a graph-based optimization that integrates well island generation, well tap insertion, and placement. Its efficacy is demonstrated within a stochastic placement engine. Experimental results show that this approach generates better area, wire length and performance metrics than traditional methods, at the cost of a marginal runtime degradation.

Placement algorithms for analog circuits explore numerous layout configurations in their iterative search. To steer these engines towards layouts that meet the electrical constraints on the design, this work develops a fast feasibility predictor to guide the layout engine. The flow first discerns rough bounds on layout parasitics and prunes the feature space. Next, a Latin hypercube sampling technique is used to sample the reduced search space, and the labeled samples are classified by a linear support vector machine (SVM). If necessary, a denser sample set is used for the SVM, or if the constraints are found to be nonlinear, a multilayer perceptron (MLP) is employed. The resulting machine learning model demonstrated to rapidly evaluate candidate placements in a placer, and is used to build layouts for several analog blocks.

Common-centroid (CC) layouts are widely used in analog design to make circuits resilient to variations by matching device characteristics. However, CC layout may involve increased routing complexity and higher parasitics than other alternative layout schemes. This paper critically analyzes the fundamental assumptions behind the use of common-centroid layouts, incorporating considerations related to systematic and random variations as well as the performance impact of common-centroid layout. Based on this study, conclusions are drawn on when CC layout styles can reduce variation, improve performance (even if they do not reduce variation), and when non-CC layouts are preferable.

We propose a complete analog mixed-signal circuit design flow from specification to silicon with minimum human-in-the-loop interaction, and verify the flow in a 12nm FinFET CMOS process. The flow consists of three key elements: neural network (NN) modeling of the parameterized circuit component, a search algorithm based on NN models to determine its sizing, and layout automation. To reduce the required training data for NN model creation, we utilize transfer learning to improve the NN accuracy from a relatively small amount of post-layout/silicon data. To prove the concept, we use a voltage-controlled oscillator (VCO) as a test vehicle and demonstrate that our design methodology can accurately model the circuit and generate designs with a wide range of specifications. We show that circuit sizing based on the transfer learned NN model from silicon measurement data yields the most accurate results.

The common-centroid (CC) layout style is widely used to minimize the impact of variations among matched devices in analog blocks such as current mirror banks and differential pairs. This paper presents a constructive, performance-aware CC placement and routing algorithm for transistor arrays. Specifically, the proposed approach maximizes diffusion sharing, incorporates length of diffusion (LOD) based stress-induced performance variations, and mitigates resistive parasitics and electromigration (EM) hotspots, all of which are critical in modern technology nodes. The proposed algorithms are validated using cell- and circuit-level test cases in a commercial 12nm FinFET process. As compared to existing works, the cells generated using the proposed approach are shown to provide better performance in the presence of systematic variations, LOD, layout parasitics, and EM-induced degradation.

The quality of layouts generated by automated analog design have traditionally not been able to match those from human designers over a wide range of analog designs. The ALIGN (Analog Layout, Intelligently Generated from Netlists) project [2, 3, 6] aims to build an open-source analog layout engine [1] that overcomes these challenges, using a variety of approaches. An important part of the toolbox is the use of machine learning (ML) methods, combined with traditional methods, and this talk overviews our efforts. The input to ALIGN is a SPICE-like netlist and a set of perfor- mance specifications, and the output is a GDSII layout. ALIGN automatically recognizes hierarchies in the input netlist. To detect variations of known blocks in the netlist, approximate subgraph iso- morphism methods based on graph convolutional networks can be used [5]. Repeated structures in a netlist are typically constrained by layout requirements related to symmetry or matching. In [7], we use a mix of graph methods and ML to detect symmetric and array structures, including the use of neural network based approximate matching through the use of the notion of graph edit distances. Once the circuit is annotated, ALIGN generates the layout, going from the lowest level cells to higher levels of the netlist hierarchy. Based on an abstraction of the process design rules, ALIGN builds parameterized cell layouts for each structure, accounting for the need for common centroid layouts where necessary [11]. These cells then undergo placement and routing that honors the geomet- ric constraints (symmetry, common-centroid). The chief parameter that changes during layout is the set of interconnect RC parasitics: excessively large RCs could result in an inability to meet perfor- mance. These values can be controlled by reducing the distance between blocks, or, in the case of R, by using larger effective wire widths (using multiple parallel connections in FinFET technologies where wire widths are quantized) to reduce the effective resistance. ALIGN has developed several approaches based on ML for this purpose [4, 8, 9] that rapidly predict whether a layout will meet the performance constraints that are imposed at the circuit level, and these can be deployed together with conventional algorithmic methods [10] to rapidly prune out infeasible layouts. This presentation overviews our experience in the use of ML- based methods in conjunction with conventional algorithmic ap- proaches for analog design. We will show (a) results from our efforts so far, (b) appropriate methods for mixing ML methods with tra- ditional algorithmic techniques for solving the larger problem of analog layout, (c) limitations of ML methods, and (d) techniques for overcoming these limitations to deliver workable solutions for analog layout automation.

Automated subcircuit identification and annotation enables the creation of hierarchical representations of analog netlists, and can facilitate a variety of design automation tasks such as circuit layout and optimization. Subcircuit identification must navigate the numerous alternative structures that can implement any analog function, but traditional graph-based methods cannot easily identify the large number of such structural variants. The novel approach in this paper is based on the use of a trained graph convolutional neural network (GCN) that identifies netlist elements for circuit blocks at upper levels of the design hierarchy. Structures at lower levels of hierarchy are identified using graph-based algorithms. The proposed recognition scheme organically detects layout constraints, such as symmetry and matching, whose identification is essential for high-quality hierarchical layout. The subcircuit identification method demonstrates a high degree of accuracy over a wide range of analog designs, successfully identifies larger circuits that contain subblocks such as OTAs, LNAs, mixers, oscillators, and band-pass filters, and provides hierarchical decompositions of such circuits.

Automating analog layout is a long-standing research problem, with a history that goes back several decades. While digital design is largely automated today, analog layout has been significantly more resistant: automation has not made much headway in industry settings. There are several reasons for this, including:

Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile algorithm, applicable to a broad variety of circuits, has been elusive. This paper presents a general methodology for the automated generation of symmetry constraints, and applies these constraints to guide automated layout synthesis. While prior approaches were restricted to identifying simple symmetries, the proposed method operates hierarchically and uses graph-based algorithms to extract multiple axes of symmetry within a circuit. An important ingredient of the algorithm is its ability to identify arrays of repeated structures. In some circuits, the repeated structures are not perfect replicas and can only be found through approximate graph matching. A fast graph neural network based methodology is developed for this purpose, based on evaluating the graph edit distance. The utility of this algorithm is demonstrated on a variety of circuits, including operational amplifiers, data converters, equalizers, and low-noise amplifiers.

Analog IC placement is typically a manual process that requires strong experience and trial-and-error iterations as it produces a large impact to circuit performance in a complicated manner. Although automatic analog placement has been studied for decades, existing methods are inadequate for achieving performance comparable with manual designs. In this work, a customized graph neural network model is developed for predicting the impact of placement on circuit performance. Knowledge obtained by such a model can be transferred among different topologies of the same circuit type. Simulation results show that the proposed model is superior to a recent CNN-based work in terms of both accuracy and knowledge transfer. It also outperforms a plug-in use of graph attention network. The proposed model is further applied in analog IC placement and achieves performance similar to manual designs.

The problem of analog design automation has vexed several generations of researchers in electronic design automation. At its core, the difficulty of the problem is related to the fact that machinegenerated designs have been unable to match the quality of the human designer. The human designer typically recognizes blocks from a netlist and draws upon her/his experience to translate these blocks into a circuit that is laid out in silicon. The ability to annotate blocks in a schematic or netlist-level description of a circuit is key to this entire process, but it is a process fraught with complexity due to the large number of variants of each circuit type. For example, the number of topologies of operational transconductance amplifiers (OTAs) easily numbers in the hundreds. A designer manages this complexity by dividing this large set of variants into classes (e.g., OTAs may be telescopic, folded cascode, etc.). Even so, the number of minor variations within each class is large. Early approaches to analog design automation attempted to use rule-based methods to capture these variations, but this database of rules required tender care: each new variant might require a new rule. As machine learning (ML) based alternatives have become more viable, alternative forms of solving this problem have begun to be explored.

This paper presents analog layout automation efforts under the ALIGN ("Analog Layout, Intelligently Generated from Netlists") project for fast layout generation using a modular approach based on a mix of algorithmic and machine learning-based tools. The road to rapid turnaround is based on an approach that detects structure and hierarchy in the input netlist and uses a grid based philosophy for layout. The paper provides a view of the current status of the project, challenges in developing open-source code with an academic/industry team, and nuts-and-bolts issues such as working with abstracted PDKs, navigating the "wall" between secured IP and open-source software, and securing access to example designs.

Stochastic computing (SC) is a promising technique for applications that require low area overhead and fault tolerance, but can tolerate relatively high latency. In the SC paradigm, logical computation is performed on randomized bit streams. In prior work, streams were generated with linear feedback shift registers; these contributed heavily to the hardware cost and consumed a significant amount of power. This paper introduces a new approach for encoding signal values: computation is performed on analog periodic pulse signals. Exploiting pulse width modulation, time-encoded signals corresponding to specific values are generated by adjusting the frequency and duty cycles of pulse width modulated (PWM) signals. With this approach, the latency, area, and energy consumption are all greatly reduced. Experimental results on image processing applications show up to 99% performance speedup, 98% saving in energy dissipation, and 40% area reduction compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy-efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

This paper describes novel design techniques for optimizing the switched-capacitor array in a wide tuning range LC VCO. The switches in the capacitor array are optimally sized to maximize the tuning range. Additionally, parasitic interconnect inductance inherent in the capacitor array is used for increasing the equivalent capacitance value. Based on these proposed techniques, an LC VCO that achieves 157% frequency tuning range from 850MHz to 7.1GHz with phase noise between -107.1 and -119.1 dBc/Hz at 1MHz offset and power dissipation between 3 and 15 mW is designed. The power and phase noise performance of this VCO is at par with the best wideband solutions. However, this is, by far, the largest tuning range obtained for CMOS LC VCOs till date.

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-mu m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11times boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.

This paper presents the design of a 12 Gbps multi-lane231- 1pseudo-random binary sequence (PRBS) generator in 0.18μm TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to theftof the process. In order to operate at frequencies higher than the limit imposed by theftof the PMOS devices, the PRBS uses current-mode logic (CML) multiplexers (MUX) with modified active inductors, resulting in an improved large-signal behavior. As the architecture of choice for the PRBS generator, we chose to generate four sub-sequences at 3 Gbps and multiplex them up to obtain a 12 Gbps data stream. Furthermore, we multiplexed delayed versions of the 3 Gbps sub-sequences to obtain multiple non-correlated versions of the231- 1pseudo-random sequence. A prototype was implemented in 0.18μm TSMC process. The high-speed CML MUX consumes 4 mA off a 1.8 V power supply, while the CMOS latch clocked at 1.5 GHz with an activity factor of 100% consumes 1 mA. The CMOS core consumes 340 mA and the CML circuitry consumes 32 mA per lane.

The functional performance of switched capacitor circuits is directly affected by variations in capacitor ratios. We have proposed techniques to accurately measure these capacitor ratios. In this paper we develop an optimal procedure to minimize the number of capacitor ratios that need to be measured while still maintaining the desired fault coverage. We make use of the sensitivity of individual performance specifications to specific capacitor ratios. The procedure has been validated with a number of examples including a first order lossy integrator a second order low-pass filter and sixth order high Q bandpass filter. The procedure developed in this paper can easily be extended to include other switched capacitor circuits.

Voltage-controlled oscillators are widely used circuit blocks, particularly in phase-locked loops. As CMOS is the technology of choice for many applications, CMOS oscillators with low phase noise and timing jitter are highly desired. CMOS ring oscillators with five different delay cell topologies have been designed, fabricated and evaluated for phase noise performance. Our results show that ring oscillators with linear loads provide much better phase noise performance than oscillators with nonlinear loads. We also observe that well designed single-ended oscillators have phase noise that is on par or better than oscillators with fully differential delay stages. Both our analysis and measurement results suggest that large signal voltage swing and improved linearity of the delay cells help reduce oscillator phase noise.

This paper describes a 1 GHz differential to single-ended amplifier for instrumentation. The unity gain amplifier can directly drive a 50 /spl Omega/ load with a common-mode voltage centered at ground and can accept up to a 1 V/sub P-P/ input signal. The measured noise floor is below 20 nV//spl radic/Hz for most of the bandwidth and the common-mode rejection is 20 dB at 1 GHz.

In this paper we present an analytical model for charge injection in MOS switches that is valid for all regions of operation. The model is general and can be applied for different load conditions. We analyze and develop two separate charge injection models for the different operating conditions. A simple continuous model that is valid for all conditions is then stitched together using appropriate functions. Simulation results from this model agree well with previously published measurement results. The model is used to predict charge injection error and nonlinearity.

This paper presents a design for an ASK-based IF-stage. This IF-stage was designed as part of a single-chip ISM band short range wireless telemetry system. The design was fabricated in 0.5 /spl mu/m CMOS process. Two main components of the IF-block are discussed in this paper. Measurement and simulation results are provided for the AGC circuit and the ASK detector. The measured dynamic range for the AGC is 40 dB at a 10 MHz IF frequency. The ASK detector was designed to operate at 1 Mb/s for the same IF frequency. A fully differential signal path is maintained throughout the design to reduce the impact of substrate and supply fluctuations. Measurement and simulation results are presented to verify the design.

This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.

Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration it is used in.We present a DFT scheme that offers the accuracy needed to test high-quality circuits.The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors.The circuit is used to completely characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios.In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy, and filter parameters can be shown to be satisfied to within 0.1% accuracy.A filter can be shown to satisfy all its functional specifications through this characterization process.We believe the accuracy of our scheme is at least an order of magnitude greater than that offered by any other scheme reported in the literature.

{ Analog IC test occupies a signi cant fraction of the design cycle.Testing costs are increased by the twin requirements of high precision and accuracy in signal measurement.We discuss a system level ACOB technique for fully dierential analog ICs.Our test techniques incorporate analog speci c constraints such as device matching, and circuit and switching noise.They have a minimal impact on performance, area and power.The techniques can be used for both discrete and continuous time circuits, over a wide frequency range.The system level DFT scheme is also used to design a self-testing switched capacitor lter.Our checking scheme provides signi cant fault coverage and is demonstrably superior to other DFT techniques for dierential circuits.

The settling behavior and power consumption of dynamic opamps are considered. The dynamic opamp is compared with a class A opamp for different clock frequencies. A single pole model in a closed loop configuration is used to estimate slewing and settling behavior. SPICE simulation results agree with theoretical predictions. It is shown that for the same power consumption dynamic opamps settle much faster than class A opamps. Dynamic opamps are particularly well suited for ultra low power switched-capacitor designs.

The design of it 6-bit 50 MHz CMOS-current-subtracting two-step flash A/D converter in 1.2 /spl mu/m CMOS technology is described. The two-step current-subtracting technique reduces the number of current comparators and their resolution requirements thus reducing both area and power. A new design for a high speed current subtracter is presented. A differential positive feedback technique is used in the current comparators to increase speed while maintaining high resolution. The complete A/D converter, including encoding logic, operates at 50 MHz and dissipates a maximum of 25 mW.>

In addition to the traditional problems associated with testing ICs, analog circuit test is very susceptible to measurement induced errors. Precise calibration and signal matching are necessary to minimize these errors. These constraints increase the complexity and cost of analog circuit testers. In this paper, we introduce analog circuit observer blocks (ACOBs). ACOBs are designed to simplify test result observation in analog and mixed-signal ICs. Measurement errors are minimized since ACOBs are better matched to the circuits being tested and impose a lower load as well. If successful, they can reduce tester complexity. We present designs for ACOBs for a fully differential operational amplifier and a pipelined A/D converter.>

A hierarchically structured framework for analog circuit synthesis is described. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described that select from among alternate design styles and translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation and from actual fabricated analog ICs based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits.>

Mechanisms needed to meet stringent performance demands in a hierarchically structured analog circuit synthesis tool are described. Experiences with adding a high-speed comparator design style to the OASYS synthesis tool are discussed. It is argued that design iteration (the process of making a heuristic design choice, following it through to possible failure, then diagnosing the failure and modifying the overall plan of attack for the synthesis) is essential to meet such performance demands. Examples of high-speed comparators automatically synthesized by OASYS are presented. Designs competitive in quality with manual expert designs, e.g. with response time of 6 ns and input drive of 1 mV, can be synthesized in under 5 seconds on a workstation.>

Experimental results obtained with OASYS, a behavior-to-structure synthesis tool for analog circuits, are described. In particular, measurements from fabricated analog ICs based on OASYS-synthesized designs are presented, and used to verify that OASYS is capable of producing real, functional circuits. Possibilities for automatically exploring the space of designable analog circuits, an ability made possible by a fast, automatic synthesis tool such as OASYS, are also described. Examples of using OASYS to explore tradeoffs among process and performance specifications are presented.>

An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.