In this paper, we present a 36 μW continuous-time Zoom (CT-Zoom) ADC with the switched resistor (SR) technique to reduce both the noise and area. The proposed CT-Zoom ADC effectively reduces in-band flicker noise using a chopped negative-R, and then further reduces in-band thermal noise by half through the use of the SR technique. This method halves the resistor in the first integrator, effectively solving the problem of thermal noise in CT-Zoom ADCs with a low-frequency signal bandwidth. The proposed dynamic CT-Zoom ADC exhibits post-layout simulation results with a peak signal-to-noise ratio (SNR) of 108.0 dB, a peak signal-to-noise and distortion ratio (SNDR) of 103.9 dB, and a total power consumption of 36 μW using a 1 V power supply, at a sampling frequency of 1.28 MHz for a 5-kHz signal bandwidth. The circuit was designed and simulated using the 28-nm CMOS process.

This paper presents an NMOS low dropout (LDO) regulator with a high-power supply rejection ratio (PSRR) and low quiescent current that uses an intrinsic gain-tracking ripple cancellation (IGTRC) technique with an adaptive biasing scheme. The proposed LDO is fabricated using a 180 nm CMOS process and achieves a quiescent current of$3.7~\mu $A with superior figure-of-merits (FOMs) of 7.6E9 (FOM1) and 0.005 ps (FOM2).

This paper presents a continuous-time delta-sigma modulator (CTDSM) for applications that require a 5-kHz signal band and high resolution. The number of applications that use negative-R to compensate for the DC-gain, unity gain bandwidth (UGB), and noise of operational amplifiers (op-amps) is increasing. However, due to process-voltage-temperature (PVT) variations, conventional negative-R has limitations in providing ideal compensation. Therefore, this paper presents an auto-tuning (AT) negative-R that can automatically calibrate for PVT variations, overcoming the limitations caused by mismatching issues in conventional negative-R. The proposed single-bit 3rd-order CTDSM applies AT negative-R to the first integrator, resulting in consistent and optimal integrator performance. The designed CTDSM was successfully fabricated in a 28-nm CMOS process and achieved the following measurement results: a peak signal-to-noise ratio (SNR) of 92.41 dB, a peak signal-to-noise and distortion ratio (SNDR) of 90.91 dB, a dynamic range (DR) of 95 dB, total power consumption of 24$\mu$W (at a supply voltage of 1 V), and a signal bandwidth of 5 kHz.

In this paper, we present a 860.8-nW low-power third-order single-bit continuous-time delta-sigma modulator (CTDSM) for sensor applications. The proposed CTDSM decrease the power consumption of the first integrator OTA by reducing the equivalent load capacitor of the first integrator using the switched resistor technique. Unlike conventional CTDSMs, switched resistor technique can reduce the size of resistors and capacitors used as integrator coefficients by using clock duties of 25% and 75%. This method solves the problem of resistor and capacitor sizing in CTDSMs that have a low-frequency signal bandwidth. The proposed low-power CTDSM exhibits a peak signal-to-noise ratio (SNR) of 85.6 dB, a peak signal-to-noise and distortion ratio (SNDR) of 84.1 dB, and a total power consumption of 860.8 nW using a 1.6 V power supply. In addition, the simulation results revealed an SNDR of up to 84.1 dB at a sampling frequency rate of 64 kHz for a 250-Hz signal bandwidth. The circuit was designed and simulated using the$0.18-\mu\mathrm{m}$CMOS process.

This paper presents an efficient approach to testing on-chip analog to digital converters (ADCs) and digital to analog converters (DACs) in loop-back mode. On-chip digital signal processing units can be used to generate stimuli. With this methodology, go/no-go tests as well as characterization of the individual ADCs and DACs are possible. The proposed approach is simple and overcomes the low parametric fault coverage of conventional loop-back tests. Simulations on a Matlab model of loop-backed converters are presented to validate the feasibility of the method.

A low-cost and comprehensive built-in self-test (BIST) methodology for analog and mixed-signal circuits is described. We implement a time-division multiplexing (TDM) comparator to analyze the response of a circuit under test with minimum hardware overhead. The TDM comparator scheme is an effective signature analyzer for on-chip analog response compaction and pass/fail decision. We apply this scheme to an oscillation-test environment and implement a low-cost and comprehensive vectorless BIST methodology for high fault and yield coverage. Our scheme allows a tolerance in the output response, a feature necessary for analog circuits. Both oscillation frequency and oscillation amplitude are measured indirectly to increase the fault coverage. We provide a theoretical analysis of the oscillation that explains why the amplitude measurement is essential. Simulation results demonstrate that the proposed scheme can significantly reduce test time of the oscillation-test while achieving higher fault coverage.

A new verification technique for /spl Delta//spl Sigma/ analog-to-digital converters (ADC) is proposed. The ADC is partitioned into functional blocks, and adaptive regression models for each partition are constructed using transistor-level simulation data. Non-idealities in circuit behavior are captured by the adaptive regression technique from the collected data. The algorithms have been implemented in a simulation program ARSIM (Adaptive Regression Simulator), which performs data sampling, model building, and simulation. Experimental results using ARSIM are shown on a second-order /spl Delta//spl Sigma/ modulator, and they demonstrate the effectiveness of our technique as a fast and accurate approach for verifying /spl Delta//spl Sigma/ converters.

We propose a comprehensive built-in self-test (BIST) methodology for analog and mixed-signal circuits. A time-division multiplexing (TDM) comparator scheme was proposed as an effective signature analyzer for on-chip analog response compaction and pass/fail decision with minimum hardware overhead. By applying this scheme to the oscillation-based test, the oscillation frequency can be measured indirectly as well as the oscillation amplitude to increase the fault coverage. The experimental results demonstrate that the proposed scheme can significantly reduce test time of the oscillation-based test with higher fault coverage.

A new technique is proposed to analyze and compress the output responses from analog circuits. We first describe the subband filtering scheme to decompose responses from the analog circuit under test (CUT). A subband filter or wavelet takes the response, then generates the decomposed signals for each frequency band. The decomposed signal for each frequency band is fed into its respective integrator. Two kinds of wavelets are used to decompose the test response and effectively detect the faults in the circuit. Implementation issues including hardware overhead are also discussed.

The partitioning in hierarchical trees (SPIHT) algorithm for wavelet-based image coding, suggested by Said and Pearlman (1996), achieves excellent rate-distortion efficiency while retaining an attractive embedded code property useful for progressive transmission. In the present work we investigate several alternative set partitioning coding strategies in an effort to improve upon SPIHT. The general thrust of our research aims at increasing the size of the sets for which coefficient significance information is efficiently transmitted. While we suggest several novel coding ideas for achieving this objective, the resulting method is not found to provide a performance advantage over SPIHT. Some explanation for this observed performance is then provided.