Demo Data from EDBT 2026 / reviewers in the wild / expert
Yiyang Zhang 0006
dblp:22/2901-6
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0001-7520-7730ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › neural network hardware › brain-inspired computing accelerator
hyperdimensional computing accelerator |
0.8 | 1 | 2024 | VAE-HDC: Efficient and Secure Hyper-dimensional Encoder Leveraging Variation Analog Entropy · DAC 2024 |
Methods — techniques the papers use, named apart from their topics
variation-based analog entropy · 1.5hyperdimensional computing · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | VAE-HDC: Efficient and Secure Hyper-dimensional Encoder Leveraging Variation Analog EntropyabstractHyperdimensional computing (HDC) is a bio-inspired machine learning paradigm utilizing hyperdimensional spaces for data representation. HDC significantly improves the ability to learn from sparse data and enhances noise robustness, and also enables parallel computation. Despite these advantages, HDC's reliance on high dimensionality and operational simplicity can lead to increased hardware costs and potential security vulnerabilities. This paper introduces a novel HDC encoding strategy using variation-based analog entropy (VAE), aiming to reduce memory footprint, lower power/energy consumption, and enhance security with physically-unclonable entropy generation. The VAE cell, with high entropy robustness (30.23 -- 57.76 dB SNR) and a small footprint (10 transistors), allows HDC to achieve a 14.3× reduction in vector dimensions, a 4.4× decrease in unit entropy cell area, and a 2% increase in accuracy compared to binary/multi-bit HDC. These benefits lead to a 1.3 -- 4.4× area and a 327× leakage power reduction when compared to an SRAM baseline. We have designed custom low-power circuits that enable end-to-end analog entropy storage, distribution management, binding, permutation, and bundling. This analog implementation prevents data conversion during feature vector encoding, thereby significantly enhancing energy efficiency (48.5nJ per query). Furthermore, with hardware-secured basis vectors, data security is significantly improved, as evidenced by the markedly degraded visual distinguish-ability of retrieved image data and maximum of 11 dB lower PSNR. Boyang Cheng, Steven Davis, Zephan M. Enciso, Yiyang Zhang 0006, Ningyuan Cao |
DAC | 5 |