Solar observations specifically allow one to determine stratifications of atmospheric properties in detail from studying spectra at a high spectral and temporal resolution. In this paper, we present a hardware accelerated framework for solar spectral analysis that includes a parameterized matched filter IP core. Our proposed hardware accelerated framework is able to process a three dimensional data cube of 700,000 spectra to find the best fit to the observation from an archive of 240,000 pre-calculated spectra in less than 3 minutes. This is almost 241 times faster than a similar software based analysis running on standard quad core machine and roughly about 10 times faster than running on GTX 1050 Ti GPU with 768 CUDA cores.

This paper presents a novel algorithm that achieves high performance in leukocytes detection and segmentation in microscopic blood sample images. To the best of our knowledge, this algorithm is the first that exploits the correlation between two CMYK and RGB color models. Our proposed algorithm uses the upper and lower limits of the pixel intensity in the Magenta component from the CMYK color space to adjust the image contrast in the Green component of the RGB image to segment the nuclei without any pre-processing steps. The proposed algorithm was tested using a series of 30 blood sample images with different color tones, image resolutions, magnifications, and surrounding conditions. The segmented nuclei are virtually congruent to the nuclei in the original image, in term of shape and area, regardless of the type of nucleus. The overall segmentation accuracy achieved by the proposed algorithm is 98.99%, with a consistent performance for the same image resolution regardless of the number of nucleus in the blood smear image. Our algorithm can be seen as a stepping stone for efficient implementations of nucleus classification to identify and classify the type of leukocyte for accurate medical diagnosis.

The emergence of smart cameras has been fueled by increasingly advanced computing platforms that are capable of performing a variety of real-time computer vision algorithms. Smart cameras provide the ability to understand their environment. Object detection and behavior classification play an important role in making such observations. This paper presents a high-performance FPGA implementation of a generalized parts-based object detection and classifier that runs with capability of 266 frames/sec. The detection algorithm is easily reconfigured by simply loading a new representation into on-board memory, i.e., the FPGA can detect and classify a newly specified object and behavior without any changes to the hardware implementation.

Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communication, it is important to understand the trade-offs in designing a matrix inversion core on an FPGA. This article describes a matrix inversion core generator tool, GUSTO, that we developed to ease the design space exploration across different matrix inversion architectures. GUSTO is the first tool of its kind to provide automatic generation of a variety of general-purpose matrix inversion architectures with different parameterization options. GUSTO also provides an optimized application-specific architecture with an average of 59% area decrease and 3X throughput increase over its general-purpose architecture. The optimized architectures generated by GUSTO provide comparable results to published matrix inversion architecture implementations, but offer the advantage of providing the designer the ability to study the trade-offs between architectures with different design parameters.

This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the parallelized architecture of multiple classifiers can have 3.3times performance gain over the architecture of a single classifier and an 84times performance gain over an equivalent software solution.

This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the optimization of the proposed architecture which can be scalable for configurable devices with variable resources. The proposed architecture for face detection has been designed using Verilog HDL and implemented in Xilinx Virtex-5 FPGA. Its performance has been measured and compared with an equivalent software implementation. We show about 35 times increase of system performance over the equivalent software implementation.

Cooperative MIMO is a new technique that allows disjoint wireless communication nodes (e.g. wireless sensors) to form a virtual antenna array to increase bandwidth, reliability and/or transmission distance. It differs fundamentally from other MIMO communication since the signals received from each node have a relative timing and frequency offset due to the distributed nature of their transmitting antennas. Therefore, the receiver must estimate the timing and frequency for each transmitting node, in addition to the MIMO channel. In this paper, we design and implement a receiver for the cooperative MIMO problem using reconfigurable hardware. We discuss the computation required for each stage of the receiver and perform experimental study of the tradeoffs between area, power, performance and quality of results. The end result is an efficient, parameterizable, cooperative MIMO receiver implemented on several different state-of-the-art FPGAs devices.

The authors consider a system architecture whereby orthogonal space time block codes (OSTBCs) are applied to a distributed set of wireless nodes. The utility offered is that by employing diversity we are able to greatly reduce the necessary link margin usually required to combat fast fading. A distributed set of wireless nodes are particularly well suited for this task as they are typically separated with significant inter-node distance thus having highly uncorrelated channels to a collector. In a typical application, a wireless sensor network (WSN) will have nodes that may wish to transmit data to a possibly mobile standoff collection point. In this paper, the authors discuss many practical aspects necessary for a real-world implementation including time and frequency offset estimation as well as channel tracking. As the waveform has been targeted to field programmable gate array (FPGA) hardware, we look at the relative implementation complexity of each signal processing element.

Distributed Arithmetic based methods are commonly used to implement Digital Signal Processing (DSP) functions such as filters and transforms. These techniques are very efficient for serial implementation of these functions, but occupy large area when fully parallel implementations for high sample rates are required.We present a method for implementing high speed Finite Impulse Response (FIR) filters using just registered adders and hardwired shifts. We extensively use common subexpression elimination to reduce the number of adders. Furthermore, we present a new technique to reduce the number of latches required in the design. We compare our designs with those produced by Xilinx CoregenTM and we observe up to 50% reduction in the number of slices for fully parallel implementations. We also observed an average performance improvement of 21.6%.

A cooperative MIMO network is considered with Ns sensors and a collector node with Mc antennas. In a practical implementation of this network, the sensor carriers have relative frequency offsets which must be estimated along with the MIMO channel. Generalized successive interference cancellation (GSIC) is proposed for this joint estimation problem. The primary operations in GSIC are correlation, FFT and cancellation. A reconfigurable hardware (FPGA) implementation of these GSIC primitives is described. A hybrid analysis/simulation for bit error rate (BER) is presented with results for GSIC using Alamouti and G4ccodes.

We present a method for implementing high speed finite impulse response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common subexpression elimination algorithm to reduce the number of adders. We target our optimizations to Xilinx Virtex II devices where we compare our implementations with those produced by Xilinx CoregenTM using Distributed Arithmetic. We observe up to 50% reduction in the number of slices and up to 75% reduction in the number of LUTs for fully parallel implementations. We also observed up to 50% reduction in the total dynamic power consumption of the filters. Our designs perform significantly faster than the MAC filters, which use embedded multipliers.