Article Effects of elevated temperature on tunable near-zero threshold CMOS Share on Authors: Vjekoslav Svilan Department of Electrical Engineering, Stanford University, 350 Serra Mall, Stanford, CA Department of Electrical Engineering, Stanford University, 350 Serra Mall, Stanford, CAView Profile , James Burr Sun Microsystems, 901 San Antonio Road, M/S MPK15-222, Palo Alto, CA Sun Microsystems, 901 San Antonio Road, M/S MPK15-222, Palo Alto, CAView Profile , G. Tyler Department of Electrical Engineering, Stanford University, 350 Serra Mall, Stanford, CA Department of Electrical Engineering, Stanford University, 350 Serra Mall, Stanford, CAView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 255–258https://doi.org/10.1145/383082.383153Online:06 August 2001Publication History 3citation137DownloadsMetricsTotal Citations3Total Downloads137Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

An 80,000 transistor, low swing, 32~x~32-bit multiplier was fabricated in a standard 0.35μm,Vth=0.5 V CMOS process and in a 0.35μm, back-bias tunable, near-zero Vth process. While standard CMOS atVdd=3.3 V runs at 136 MHz, the same performance can be achieved in the low- Vth version at Vdd=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-Vth version is able to run at 188 MHz, which is 38% faster than standard CMOS.

Describes a special purpose, very high speed, digital deterministic Boltzmann neural network VLSI chip. Each chip has 32 physical neural processors, which can be apportioned into an arbitrary topology (input, multiple hidden and output layers) of up to 160 virtual neurons total. Under typical conditions, the chip learns at approximately 5*10/sup 8/ connection updates/second (CUPS). Through relatively minor (subsequent) modifications, the authors' chips can be 'tiled' in multi-chip modules, to make multi-layer networks of arbitrary size suffering only slight communications delays and overhead. In this way, the number of CUPS can be made arbitrarily large, limited only by the number of chips tiled. The chip's high speed is due to massively parallel array computation of the inner products of connection weights and neural activations, limited (but adequate) precision for weights and activations (5 bits), high clock rate (180 MHz), as well as several algorithmic and design insights.>

Multichip modules permit highly efficient implementation of tiled architectures. If the tiles are implemented in submicron CMOS, extremely highly computation rates can be achieved, but power dissipation becomes the principal factor limiting achievable levels of integration and performance. Some examples of tiled architectures are described. The feasibility and advantages of reduced voltage operation for reducing energy per operation in power constrained environments are discussed.>