We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.

A novel approach for the lossless compression of images is presented. After preprocessing, the image is split into bit planes which are then divided into smaller blocks. Mixed blocks are converted to Boolean switching functions and then subjected to minimization to arrive at a compact representation, leading to possible data compression. Blocks are then classified into distinct events based on the outcome of logic minimization. A Huffman code is constructed and the blocks are encoded suitably. This approach provides a framework to incorporate various possible switching theoretic techniques into the basic coding scheme proposed by us. This paper also shows that logic minimization can be used to handle blocks of larger size, than practically possible with Huffman coding, to yield significant compression on gray-level images. Our approach compares well with JPEG in terms of compression ratio.

We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLAs are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark PSM's from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS'89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests.

In recent correspondence, L. Ye-Wei and J. Wei (see ibid., vol.C-35, p.930-1 (1986)) have shown two counterexamples that contradict theorems four and five of a paper by J.E. Smith (see ibid., vol.C-28, p.845-53 (1979)). In his reply, Smith (see ibid., vol.C-35, p.931 (1986)) stated an additional condition under which the theorems hold good. The commenters provide a counterexample that contradicts Smith's modified theorem five. They provide another counterexample that contradicts theorem three of Smith's original paper. In his reply, Smith corrects an error in his treatment.>