Neuromorphic computing achieves highly energy-efficient computations while adapting to environmental changes. Processing time series data by spiking neural networks can further reduce the power consumption of neuromorphic computing devices because most of the energy in the network is consumed only when the neuron generates and transmits a spike. In this study, we designed fully analog two-variable spiking neuron and spiking neural network circuits, taking advantage of the physical properties of transistors as analog devices. The energy consumption of the circuit for generating a spike was 22.7 fJ/spike when the MOS transistors were operating in the subthreshold region. The proposed circuits were implemented on an analog very large-scale integrated (VLSI) circuit chip in a$0.18~\mu $m CMOS process. The circuits exhibit complex spike dynamics even under subthreshold operation according to chip measurements. We demonstrated that the spike sequence generated by the spiking neural network circuit was successfully applied to spoken digit recognition tasks via a reservoir computing framework with 14.4 fJ/SOP efficiency. These results provide important insights into edge AI applications of SNN-based neuromorphic hardware.

Edge computing requires low-power, real-time processing of complex information. Spiking neural networks are highly expected to be applied to edge computing due to their efficient computing properties. Here, we design a mixed-signal LSI consisting of an analog spiking neural network and digital inference circuits for edge device. The two-variable spiking neuron circuits operate in an analog manner using the physical properties of transistors and are connected through synaptic circuits to form a network. The neural network successfully operates and exhibits complex nonlinear behavior in response to external inputs. The power consumption of the spike generation is as low as tens of femtojoules per spike because the transistors in the circuits operate in the subthreshold region, which is enough to be used as edge computing devices. In addition, a digital circuit was designed to perform real-time inference using the spiking sequences from the analog spiking neural network. The result showed that the mixed-signal LSI consisting of the analog spiking neural network and the digital inference circuits can be applied to the spoken digit classification task in real time. The proposed system has the potential to be used as ultra-low-power neuromorphic hardware in practical applications.

Biological neural networks are well known for their capacity to process information with extremely low power consumption. Fields such as Artificial Intelligence, with high computational costs, are seeking for alternatives inspired in biological systems. An inspiring alternative is to implement hardware architectures that replicate the behavior of biological neurons but with the flexibility in programming capabilities of an electronic device, all combined with a relatively low operational cost. To advance in this quest, here we analyze the capacity of the HEENS hardware architecture to operate in a similar manner as an in vitro neuronal network grown in the laboratory. For that, we considered data of spontaneous activity in living neuronal cultures of about 400 neurons and compared their collective dynamics and functional behavior with those obtained from direct numerical simulations (in silico) and hardware implementations (in duris silico). The results show that HEENS is capable to mimic both the in vitro and in silico systems with high efficient-cost ratio, and on different network topological designs. Our work shows that compact low-cost hardware implementations are feasible, opening new avenues for future, highly efficient neuromorphic devices and advanced human-machine interfacing.

Edge computing requires the processing of real-time and personalized information with low power consumption. Neuromorphic devices are promising candidates for applications related to edge computing. Rate neurons, which are typically used in neuromorphic hardware, persistently consume power regardless of their outputs. To further reduce the power consumption of neuromorphic devices, spiking neurons are more suitable because they are event-driven, and information is transferred only when the neuron fires. Herein, we propose a two-variable spiking neuron circuit that operates in a fully analog manner by utilizing the physical properties of transistors as analog devices. By operating in the subthreshold region of the MOS transistor, the energy required to produce a spike is approximately tens of fJ/spike. Furthermore, the analog neuron can exhibit complex spike dynamics, such as chattering, as confirmed using post-layout simulations. The simulations indicated that a neural network comprising the proposed neuron circuits operates successfully and exhibits complex nonlinear behavior. These results provide a basis for dedicated hardware spiking neuron circuits, which could be used as ultra-low-power neuromorphic hardware in various applications, such as realizing liquid-state machines for processing time-series signals.

This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.

Optical energy harvesting enables the development of autonomous microsensor networks. The harvest-use approach applied to monolithic standard bulk CMOS is simple but suffers from the low-voltage issue of single photodiode as a voltage supply. It is overcome by using the LCMOS approach with complementary voltage generation, thus achieving a usable supply around 900 mV. Guidelines to develop analog circuits with this approach are provided. Power supply, references and folded cascode amplifier design are introduced. Simulation results for TSMC 0.18 μm are provided and applications in the area of integrated sensors are pointed out.

A spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input sensor processing system for environment perception applications. The analog front-end encodes the input signal in a signed spike representation, which is further processed by means of a digital Spiking Neural Network (SNN) on a Single-Instruction Multiple-Data (SIMD) multiprocessor. The spike distribution for both systems is based on Address-Event Representation (AER) scheme, asynchronous for the Analog Pre-Processor (APP) and synchronous for the Digital Multi-Processor (DMP), synchronized by means of an AER transceiver. A proof-of-concept application of the system being able to process sensory information has been demonstrated. The system utilizes 30-neurons emulated by the DMP to process spike-encoded information provided by its analog counterpart, enabling the feature extraction of the input signal. The frequency detection capability of the system is experimentally reported.

LCMOS, a harvest-use light-powered scheme for standard CMOS circuits based on photogenerated currents in the drain-substrate PN junction of both PMOS and NMOS transistors is introduced. PMOS and NMOS bulks are ground-connected so the generated currents induce symmetrical positive and negative voltage at the PMOS and NMOS sources, respectively. Applying this approach to a CMOS inverter ring oscillator in 150 nm technology, simulations show that nearly 1 Vpp signal range can be obtained. The operation of a simple 4-bit counter is also illustrated. The light-powering technique can be applied almost directly to digital standard cells in ultra-low-power applications with modest processing speed requirements.

A mixed-signal continuous-time-processing standard CMOS implementation of an asynchronous sigma-delta modulator aimed to drive a switching amplifier operating as an on-chip wideband adaptive power supply is presented in this work. The paper first briefly discusses the fundamental limit tracking capabilities of a two-level switching signal to inband- error-free track a bandlimited signal with minimum average switching frequency. It is argued the adequacy of an adaptive asynchronous sigma-delta modulator (AAΣΔ) to approximate such fundamental characteristics. The second part of the paper presents mixed-signal design details of the various subcircuits implementing a CMOS low-power digitally-programmable AAΣΔ modulator, with 7 MHz average switching frequency operation and 1000 μm × 640 μm area occupancy.

This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler, UbiAssembler), allowing respectively to extract, compile and assemble parallelizable parts of applications described in Jubi language. Jubi is a modified Java agent based language (JADE) dedicated to the Ubichip (the bio-inspired chip developed within the confines of the Perplexus project). By appending hardware directives to a software agent description, the inherent flexibility of software is combined with the runtime performance of a hardware execution. In the case of typical Perplexus applications such as the spiking neural network simulator, this contribution takes profit of the intrinsic property of the Ubichip in terms of parallelism resulting in an expected speedup of at least one order of magnitude. Finally, this hybrid (SW/HW) flow could be easily modified and adapted to support other kind of distributed platforms.

SpiNDeK (spiking neural network design kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are reported, regarding the generation of connections as well as synapse and neuron parameters of spiking neural networks as well as the automated code generation and simulation, ready to be executed by an ad-hoc parallel architecture. The tool is fully functional and has demonstrated its usefulness.

In this paper we shall present a reconfigurable architecture that has been specifically conceived for emulating large-scale bio-inspired systems. The architecture is organized as a regular array of programmable elements that can be used either as fine grain logic elements or configured in order to construct massively parallel SIMD (single instruction multiple data) machines. As it will be explained, the specific features that have been included in the architecture permit the efficient implementation of a wide range of complex systems.

In this paper we show a low power and very compact VLSI implementation of a FitzHugh-Nagumo neuron for large network implementations. The circuit consists of only 17 small transistors and two capacitors and consumes less than 23 muW. It is composed of a nonlinear resistor and a lossy active inductor. We demonstrate that a simple low Q active inductor can be used instead of a complex one because the parasitic series resistor can be easily embedded to the FitzHugh-Nagumo model. We also perform a statistical analysis to check the robustness of the circuit against mismatch.

In this paper, a simple, fully digital, asynchronous finite state machine controller for buck-boost power converters is introduced and simulated. With the addition of only two analog voltage comparators and six power MOS switches, the circuit can generate an output voltage that is able to track a dynamic reference with a 1 MHz bandwidth with good efficiency using a 0.35 mum CMOS process. The controller also provides adiabatic charging and discharging of capacitive loads.

A method for controlling position, damping and inertia in parallel-plate electrostatic actuators is proposed. This method overcomes the pull-in effect and the limitations produced by the parasitic capacitances without requiring any additional electrodes or position sensors. It forces the actuator to behave like a linear second-order system with full control of the dynamics, being able to electronically adapt the mass and damping coefficients for a better performance for each particular application. A continuous-time, analog linearization law, feasible to be implemented with typical blocks of analog or digital signal processing, is described and analyzed in this paper.

In this paper we present a fully CMOS-compatible circuit that extends the weak-inversion exponential characteristic of a MOS transistor to seven decades of current. This circuit can be used to implement log-domain or translinear circuits up to the strong inversion region, allowing highly-accurate implementations of translinear loop functions and higher biasing currents (and potentially higher frequency operation) than MOS weak-inversion biased log-domain circuits.

This paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, we study the microelectronic analog implementation of physical oscillators, instead of the software computer-simulated implementation. With this aim, the original oscillator has been adapted to a suitable microelectronic form. So as to study the hardware nonlinear oscillators, we propose two macro models, demonstrating that they preserve the synchronization properties. Secondary effects such as mismatch and output delay and their relation to network synchronization are analyzed and discussed. We show the correct operation of the proposed electronic oscillators with simulations and experimental results from a manufactured integrated test circuit. The proposed architecture is intended to perform the scene segmentation stage of an autonomous focal-plane self-contained visual processing system for artificial vision applications.

Using the neuromorphic approach, we propose an analog very large-scale integration (VLSI) implementation of an oscillatory segmentation algorithm based on local excitatory couplings and global inhibition. The original model has been simplified and adapted for its efficient VLSI implementation while preserving its segmentation properties. To demonstrate the feasibility of the approach, a 16/spl times/16-pixel testchip has been manufactured. Extensive experimental results demonstrate that it can properly segment binary images. Power consumption, segmentation time per cell, and system complexity are very low compared to other hardware and software implementation schemes. We also show two main differences between the original algorithm and the analog approach. First, the network is noise tolerant without the need of additional elements and second, delays between oscillators due to the combination of mismatch and output capacitances have to be accounted for network performance.

A sequentiality study for mixed-signal VLSI implementations of neuro/fuzzy feedforward algorithms is presented. Implications of sequential processing and mixed-signal operation are derived. Basic building blocks for sequential mixed-signal neural and fuzzy computing are proposed, and two example sequential processors are described. Feedback from designed processors and subcircuits allows consideration of the technology constraints for analysis and extension to different sequentiality degrees.