This paper describes an expandable digital delay line to achieve both a wide delay range and fine delay resolution. The proposed delay line has coarse and fine delay lines with almost identical unit delay cells. The coarse delay line has a classical configuration of cascaded connection for easy expansion of the delay range. The fine delay line applies phase interpolation to the signals before and after the unit delay cell for fine delay resolution. This architecture allows easy expansion of the delay range while keeping the fine resolution. The delay line also has duty cycle corrector for the clock signal using the simple structure of additional PMOS and NMOS onto the phase-mixing node. Measurement results of the test-chip show the basic concept of the proposed delay line was effective. This delay line has a well-balanced performance and achieves the finest resolution (almost half) of any published delay lines with a delay range of 1 ns or greater.

This paper describes a Fractional-N Phase Locked Loop (PLL) for multi-phase (=M) clock generation by reducing capacitor area. The M-phase clocks from the Voltage Controlled Ring Oscillator (VCO) have a frequency between N and N+1 times of a reference clock by second-order Delta Sigma Modulator (DSM). The reference clock is divided into M-phase clocks by Delay Locked Loop (DLL). The DSM assigns N or N+1 to a programmable divider (DIV), and the M DIV and DSM are prepared to feed M-phase divided VCO clocks. The divided VCO clocks and the reference clocks are compared respectively during one cycle of the input clock. This PLL system is equivalent to multiplying the input clock frequency by M, and the loop bandwidth of the PLL can be wider (×M) by reducing the capacitance value to one-Mth (÷M) in a loop filter (LF). To achieve the system, i) the divided VCO clocks should be generated by adding appropriate delay, and ii) the threshold value of each DSM has to be set properly. Measurement results of a test chip show equivalent frequency fluctuation and phase jitter of VCO clocks between conventional PLL with capacitance value C and the proposed PLL with capacitance value C÷M.

When more than one dies are stacked vertically in 3-D integrated circuits (3DICs), the overall system yield degrades significantly. While each die can be tested before stacking, failures in 3DIC interconnects could jeopardize the entire system. In this paper, a dual-mode transceiver is proposed as a built-in-self-test/repair solution to improve the yield of direct face-to-face copper thermocompression bonding (Cu-Cu bonding). The proposed transceiver could improve the Cu-Cu bonding-based interconnect reliability with the introduction of two operation modes: the ohmic mode when Cu-Cu bonding presents low resistance and the capacitive coupling mode when Cu-Cu bonding is showing any sign of failure with high resistance at the bonding interface. Such mode sensing is self-contained in the transceiver itself with the help of the proposed resistance sensor. In this paper, we discuss the modeling of Cu-Cu bonding and the proposed transceiver design with power, latency, jitter, and crosstalk simulations followed by the design guideline for the practical implementation with yield analysis.

This paper introduces a hybrid capacitive coupling interconnects (CCIs) array suitable for bumpless flip-chip 3-D integration. Inside the hybrid array, both single-ended and common-centroid differential CCIs are interleaved together to cancel the crosstalk among them. The crosstalk cancellation capability of its own allows CCIs to be placed closer and thus improves the area efficiency. A high gain and high common-mode-rejection ratio receiver is also presented to minimize the jitter caused by the common-mode noise. The process variation track biasing circuit is also proposed for the receiver. The measurement verifies that the proposed transceiver in a 3 × 3 pseudohybrid CCIs array produces only 84 ps or 0.2 unit interval crosstalk related jitter under the worst case crosstalk condition. A total of nine transceivers in the array achieve the data rate of 20.79 Gb/s and consume only 53 μW/Gb/s. The chip was fabricated in 65-nm CMOS technology.

Interconnect density in traditional capacitive coupling electrodes array is limited by capacitive crosstalk between electrodes. In this work, we propose an array structure where single-ended and differential pair electrodes (designed in the common-centroid structure) are alternatively placed horizontally and vertically. The proposed structure not only cancels out the crosstalk noise but also reduces the spacing requirement between electrodes. A novel self-biased fully differential receiver suppresses the common-mode coupled crosstalk in the differential electrodes. The receiver provides CMRR of 25dB and can recover wide band (10 kHz ~ 1 GHz) signals with 32dB gain. It consumes 25 μW at 1 GHz. It is designed and simulated in a 1.5V 0.13μm CMOS technology.

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm2in 0.13-mum CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm2. Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.