This paper analyzes the impact of simultaneous switching noise (SSN) on the timing behavior of CMOS digital blocks. The concept of instantaneous transfer function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak of noise is not relevant. The influence of structural parameters such as the block topology is evaluated, and the unpredictable aspect of SSN impact on path delay is highlighted.

Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions.

Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and I/sub DDQ/ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because art accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance and location.

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This paper introduces the use of the oscillation test technique for MEMS testing. This well-known test technique is here adapted to MEMS. Its efficiency is evaluated based on a case study: A CMOS electromechanical magnetometer.

In this paper, Oscillation-based Test Methodology (OTM) is evaluated in the context of MEMS testing. Both qualitative and quantitative evaluations of fault coverage are discussed and the impact of test on production yield is addressed. This article also introduces the Lorentz force as a low-cost stimulus for electro-mechanical structures.

This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

This paper focuses on the detectability of defects causing the gates of transistors in CMOS integrated circuits to float (open), i.e., on floating gate transistor (FGT) faults. Such faults are known to occur in practice. It is increasingly important to consider their detection to meet high quality requirements for circuits fabricated in deep submicrometer technologies. We focus on the detectability of FGT faults by the standard voltage- and current-based production test strategies that we refer to as static voltage (SV), dynamic voltage (DV), and static current (SC) test strategies. We demonstrate how the behavior of the devices caused by FGT faults depends on two classes of technological and topological parameters: the predictable and unpredictable parameters. We show that an FGT fault can induce abnormal logic values, additional delays, or increased power supply current. We introduce the concept of a detectability interval, i.e., the range of values an unpredictable parameter may assume that one allows for the fault detection using a specific test strategy. We illustrate how the detectability intervals for the SV and DV strategies complement that of the SC strategy. In addition, a new test scheme that results in an increased SC detectability of FGT faults is developed. Finally, we demonstrate the effects of initial trapped charges and the effects of coupling to surrounding metal on the detectability intervals of each of the test strategies.

This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation, validated by simulation results.

The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8/sup th/ order analog linear filter is used as an application example. The required modifications in the circuit are presented with the results in terms of area overhead and fault coverage.

The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimuli and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical hardware-consuming concurrent calculations by hardware-saving time-spread calculations. The decomposition technique is used both at high level (specific test phases are dedicated to each ADC parameter computation) and low level (sequential steps inside each test phase). Pseudo-algorithms are given to derive offset, gain error and nonlinearities.

In this paper, we present a modelling operation dedicated to animation. This operation, called thickening, is a generalization of the extrusion operation. It allows to build from a graph 3-D objects with circular section and 4-D objects with spherical or toric section. Moreover, the date and the number of mergings and splittings in the associated animation are perfectly controlled, and the trajectory of each of the animated objects is completely established. Several types of thickening are presented in this paper, to build a surface or a volume, starting from a graph drawn in a surface or in a volume. Copyright © 2000 John Wiley & Sons, Ltd.

This paper presents both the design and the characterization of a full CMOS magnetic field sensor. As an alternative to Hall effect sensors, it acts as a microscopic cantilever, deformed under the action of the Lorentz force.

This paper studies the Boolean (Static Voltage) and the I/sub ddq/ (Static Current) detection of Floating Gate faults due to large opens on transistor gate connections. We show that existing electrical models describing the behavior of FGT faults fail to allow the prediction of the floating gate potential due to the unpredictable parameters such as the initial changes and the polysilicon-to-bulk capacitance. We propose the twin-transistor structure as a basis for a general analysis of the Boolean and I/sub ddq/ detection of FGT faults. Using this analysis, optimal conditions for detection are defined for Boolean as well as I/sub ddq/ tests.

In this paper, a cost-effective DFT solution for the testing of ring oscillator-based VCOs is presented. The strategy is based on the reconfiguration concept: we propose to modify the circuit so that the VCO operates as a digital structure in test mode. The test can then be performed on a standard digital tester, avoiding the use of costly mixed-signal test equipment. In addition, simulation results show that the use of an adequate digital test strategy permits one to obtain better fault coverage than a classical functional center frequency test.

In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits one to detect faults in the block.

The paper describes an approach to optimize the application of the multi-configuration DFT technique for analog circuits. This technique allows to emulate the circuit in a number of new test configurations targeting the maximum fault coverage. The brute force application of the multi-configuration is shown to produce a very significant improvement of the original poor testability. An optimized approach is proposed to apply this DFT technique in a more refined way. The optimization problem consists in choosing among the various permitted test configurations, a set that leads to the best testability/cost trade-off. This set is selected according to ordered requirements: (i) the fundamental requirement of maintaining the maximum fault coverage and (ii) non-fundamental requirements of satisfying some user-defined cost functions such as test time, silicon overhead or performance degradation. Results are given that exhibit very interesting features in terms of either test procedure simplicity or DFT penalty reduction.

In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.

This paper demonstrates that the detection of defect depends on two classes of parameters: the predictable and unpredictable parameters. The demonstration is made with two very different types of defects (the interconnect short and the interconnect open) considering the static voltage, dynamic voltage and static current strategies. The value of the short resistance is the unpredictable parameter of the interconnect short and the polysilicon-to-bulk capacitance of the interconnect open. It is shown that any test strategy is able to detect shorts and opens each one for a given range of the unpredictable parameter called the 'analog detectability interval'. It is then demonstrated that the fundamental criterion for test strategy efficiency evaluation is the consideration of the analog detectability Intervals together with the unpredictable parameter distributions. It is finally shown that for realistic situations the voltage strategies exhibit a very good efficiency for a very reasonable cost making the use of expensive current strategy difficult to justify.

A Design-For-Testability (DFT) technique for analog circuits, called the Multi-Configuration technique is presented. This technique exhibits some flexibility features since different solutions are possible for its implementation. Different degrees of granularity are associated to the different solutions, corresponding to a given trade-off between implementation cost and test and/or diagnosis facilities. The multi-configuration technique is illustrated and validated on a 8/sup th/ order band pass filter.

This paper analyses the impact of the power supply voltage on the logical behavior of resistive Bridging Fault. It is theoretically demonstrated that the interval of resistance corresponding to the appearance of a faulty value exponentially increases when the power supply decreases. Using the Parametric Model specifically developed for resistive bridging faults, results of parametric bridging faults simulations on benchmark circuits clearly show an improvement of about 40% when a lower-than-normal power supply is used. Moreover this bridging fault coverage improvement technique doesn't need any additional effort such as Design for Testability or specific Test Pattern Generation.

The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operation, several more easily testable configurations are emulated. Different implementations are proposed for these test configurations that are shown to be useful to improve either the controllability or the observability. The efficiency of the method is evaluated in terms of fault coverage, number of modified flip-flops and test application time, using ISCAS89 benchmarks.

This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O's. The key point of this transformation is to permit each analog stage to have a test mode for which it is converted into a follower stage. Adaptative solutions are proposed depending of the availability of on-chip digital resources eventually re-usable to manage analog test. The testability cost is shown to be very low in terms of additional circuitry, number of extra pins, analog response penalty and test management. A case study is presented that demonstrates the applicability of the method.

The most recent bridging fault models, the voting and the biased voting model use the concept of relative transistor strength during fault simulation. A SPICE pre-simulation allows one to determine the relative strength of unit dimension transistors; the results stored in tables are then used during fault simulation. This concept is very efficient for single transistor and parallel transistor networks but suffers when serial transistor networks are considered. The relative strength of serial transistor networks implies the use of many tables (for 2, 3, 4, ... serial n and p transistors) slowing down the fault simulation procedure. This paper presents a new model for serial transistor networks which accelerates bridging fault simulation. This model allows one to easily define a single transistor equivalent to the serial network. In this way, any bridging fault involving any transistor network can be considered as a bridging fault involving single transistors. This model used with either the voting or the biased voting model decreases the number of required tables increasing the efficiency of the bridging fault simulation.

From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 /spl Omega/ to 500 /spl Omega/. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible, do not accurately and realistically represent the behavior of the fault. Third, a new parametric bridging fault model is proposed allowing to realistically represent the faulty behavior according to the intrinsic resistance which is not known a priori. Finally, a parametric bridging fault simulation algorithm is described together with some redefinition of the classical concepts of fault detection and fault coverage.

This paper analyses the general problem of the determination of the intermediate potentials created by a bridging fault. The analyses is made taking into account the bridge resistance value. It is shown that the fault is detectable as a logic error for a given range of bridge resistance values. But, in this range, the logic faulty value is independent of the bridge resistance value. A general electrical model which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage is proposed. A global procedure to simulate bridging fault is given. By using the proposed equations and model no SPICE simulation is required.>

Sequential ATPGs, now, are able to handle an appreciable degree of sequentiality, thus allowing to treat partial scan implementations with a suitable fault coverage. Nevertheless, with these methods the test duration remains often prohibitive due to the long scan register. The DFT method we present is based on cycle breaking and sequential depth reduction guided by graph analysis. When a flip-flop is recognized as a pertinent site for breaking cycles, its input line is disconnected. The observability and controllability losses induced by this operation are compensated by the creation of overlapping configurations guided by structural analysis. Results are presented on testability improvement. They illustrate the drastic cycle and sequential depth reduction obtained when passing from an initial circuit to its corresponding configurations. An implementation of the method using scan flip-flops as modified instances is proposed. Comparison with purely scan techniques is presented in terms of fault coverage, test length and number of modified flip-flops.>