This paper presents our work in solving one of the weakest links in 802.11-based indoor-localization: the training of ground-truth received signal strength data. While crowdsourcing this information has been demonstrated to be a viable alternative to the time consuming and accuracy-limited process of manual training, one of the chief drawbacks is the rate at which a system can be trained. We demonstrate an approach that utilizes users' calendar and appointment information to perform interactionless training of an 802.11-based indoor localization system. Our system automatically determines if a user attended a calendar event, resulting in accuracy comparable to our previously published large-scale crowdsourced deployment. We find that no other user interaction is necessary to train the system to that level of accuracy when calendar data are available. In ideal conditions, this technique can reduce training time by over a factor of six.

Mobile phone services based on the location of a user have increased in popularity and importance, particularly with the proliferation of feature-rich smartphones. One major obstacle to the widespread use of location-based services is the limited battery life of these mobile devices and the high power costs of many existing approaches.

1. SUMMARY Google's App Inventor for Android (AIA) is a visual programming environment for creating mobile phone applications that is designed to be accessible and appealing to college nonmajors taking introductory courses in computer science. Specifically, AIA provides a development environment similar to StarLogo TNG [7], Scratch [5], and Alice [2] but enabling users to create mobile applications incorporating social networking, location awareness, and Web-based services for Google's Android platform [1].

We present a parameterized stereo vision core suitable for a wide range of FPGA targets and stereo vision applications. By enabling easy tuning of algorithm parameters, our system allows for rapid exploration of the design space and simpler implementation of high-performance stereo vision systems. This implementation utilizes the census transform algorithm to calculate depth information from a pair of images delivered from a simulated stereo camera pair. This work advances our previous work through implementation improvements, a stereo camera pair simulation framework, and a scalable stereo vision core.

We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation utilizes the Census transform algorithm to calculate depth maps from a stereo pair of automotive-grade CMOS cameras. The final prototype utilizes commodity hardware, including a Xilinx Spartan-3 FPGA, to process 320times240 pixel images at greater than 150 frames per second and deliver them via a USB 2.0 interface.

In this paper, we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research which presented a methodology for optimizing the dynamic range- the most significant bit position. In this work, we present an automated optimization technique for the least-significant bit position of circuit datapaths. We present results describing the effectiveness of our methods on typical signal and image processing kernels.

We present a methodology for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research which presented a methodology for optimizing for dynamic range--the most significant bit position. In this work we define the problem of least significant bit optimization and propose optimization techniques that provide finer control of area-to-error tradeoffs than more traditional methods. We present some preliminary results describing the effectiveness of our techniques on typical signal and image processing kernels.

Currently, few tools exist to aid the FPGA developer in translating an algorithm designed for a general-purpose-processor into one that is precision-optimized for FPGAs. This task requires extensive knowledge of both the algorithm and the target hardware. We present a design-time tool, Precis, which assists the developer in analyzing the precision requirements of algorithms specified in MATLAB. Through the combined use of simulation, user input, and program analysis, we demonstrate a methodology for precision analysis that can aid the developer in focusing their manual precision optimization efforts.