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Masahiko Motoyama

dblp:22/5160 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1Security and privacy · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 73% Interconnection networks and networks-on-chip · 27%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis
public-key cryptography		 0.012001
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication · CHES 2001
Cryptographic primitives and cryptanalysis › public-key cryptography
RSA		 0.012001
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication · CHES 2001
Integrated circuit design › digital circuit design › arithmetic circuit design
modular arithmetic		 0.012001
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication · CHES 2001
Integrated circuit design › digital circuit design › arithmetic circuit design › modular multiplication
montgomery multiplication		 0.012001
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication · CHES 2001
Interconnection networks and networks-on-chip › switch architecture
buffer design		 0.011991
A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip › router architecture
shared buffer design		 0.011991
A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip
switch architecture		 0.011991
A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991
Internet architecture and protocols › ATM networks
ATM switching		 0.011991
A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

computer simulation · 0.0BiCMOS process · 0.0
YearPublicationVenuePosition
2001 Implementation of RSA Algorithm Based on RNS Montgomery Multiplication
Hanae Nozaki, Masahiko Motoyama, Atsushi Shimbo, Shin-ichi Kawamura
 CHES2
1991 A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture
abstract
The authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated.>
Yasuro Shobatake, Masahiko Motoyama, Emiko Shobatake, Takashi Kamitake, Shoichi Shimizu, Makoto Noda, Kenji Sakaue
 IEEE J. Sel. Areas Commun.2