In this article, we present a novel type of medium-grained reconfigurable architecture that we term the Field Programmable Operation Array (FPOA). This device has been designed specifically for the implementation of HLS-generated circuitry. At the core of the FPOA is the OP-block. Unlike a standard LUT, an OP-block performs multi-bit operations through gate-based logic structures, translating into greater speed and efficiency in digital circuit implementation. <?tight?>Our device is not optimized for a specific application domain. Rather, we have created a device that is optimized for a specific circuit structure, namely those generated by HLS. This gives the FPOA a significant advantage as it can be used across all application domains. In this work, we add support for both distributed and block memory to the FPOA architecture. Experimental results show up to a 13.5× reduction in logic area and a 9.5× reduction in critical path delay for circuit implementation using the FPOA compared to a standard FPGA.

As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Most current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for techniques that can trade fault tolerance for lower area penalties. Area constrained approaches accept available hardware resources as an input and outputs a partially fault tolerant circuit. The open question with these approaches is selecting the circuit subset to protect which will maximize the fault coverage. This paper presents several methodologies for selecting subsets and analyzes their performances on several circuits based on fault coverage provided and additional delay.

The ever increasing popularity of particle swarm optimization (PSO) algorithm is recently attracting attention to the embedded computing world. Although PSO is in general considered to be computationally efficient algorithm, its direct software implementation on complex problems, targeted on low capacity embedded processors could however suffer from poor execution performance. This paper first evaluates the performance of the standard PSO algorithm on a typical embedded platform (using a 16-bit microcontroller). Then, a modular, flexible and reusable architecture for a hardware PSO engine, for accelerating the algorithm's performance, will be presented. Finally, implementation test results of the proposed architecture targeted on Field Programmable Gate Array (FPGA) technology will be presented and its performance compared against software executions on benchmark test functions.

The ever increasing popularity of the particle swarm optimization (PSO) algorithm is recently attracting attention to the embedded computing world. Although PSO is considered efficient compared to other contemporary population based optimization techniques, for many continuous multimodal and multidimensional problems, it still suffers from performance loss when it is targeted onto embedded application platforms. Examples of such target applications include small mobile robots and distributed sensor nodes in sensor network applications. In a previous work we presented a novel, modular, efficient and portable hardware architecture to accelerate the performance of the PSO for embedded applications. This paper extends the work by presenting a parallelization technique for further speedup of the PSO algorithm by dividing the swarm into a set of subswarms that are executing in parallel. The underlying communication topology and messaging protocols are described. Finally, the performance of the proposed system is evaluated on mathematical and real-world benchmark functions.

Particle swarm optimization (PSO) has gained growing popularity in the recent years and is finding a wide range of important applications. Like other population based, stochastic meta-heuristics, PSO has a few algorithm parameters that need to be carefully set to achieve best execution results. This paper develops an automatic parameter tuning technique for enhancing its performance. The effectiveness of the proposed method is demonstrated on mathematical benchmark functions as well as on a real world application problem.

This paper addresses the problem of emission source localization in an environment monitored by a distributed wireless sensor network. Typical application scenarios of interest include emergency response and military surveillance. A nonlinear least squares method is employed to model the problem of estimation of the emission source location and the intensity at the source. A particle swam optimization (PSO) approach to solve this problem produces solution qualities that compete well with other best known traditional approaches. Moreover, the PSO solution achieves the best runtime performance compared to the other methods investigated. However, when it is targeted on to low capacity embedded processors PSO itself suffers from poor execution performance. To address this problem a direct, flexible and efficient hardware implementation of the PSO algorithm is developed, resulting in tremendous speedup over software solutions on embedded processors.

Partial differential equations (PDEs) are used to model physical phenomena and then appropriate convergent numerical algorithms are employed to solve them and create computer simulations. In many important applications, such as weather prediction and contaminant transport processes, simulation outputs are required in real time or even faster, yet the spatial component of the problem is very large, thereby increasing the computational time. In addition, often times numerical scientists work in groups to create a large-scale code, but they work individually on PCs to test components of the code, so that speedup of the computational algorithms on PCs is desirable. There is a benefit to creating and using custom hardware to perform the numerical calculations faster than commodity hardware. This work uses a high-level programming language (Java) to behaviorally describe, and then implement, a finite difference solution of a parabolic PDE as a custom hardware circuit targeted to an FPGA. The results show that the circuits can perform the calculations 1 to 2 orders of magnitude faster than commodity hardware.