Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Oliver Wahlen

dblp:22/5722 · DBLP profile ↗
← Back
4ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Processor architecture and microarchitecture · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › instruction set architecture
application-specific instruction-set processor
0.012001
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation › hardware/software co-design
application-specific instruction set processor design
0.012001
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Processor architecture and microarchitecture › instruction set architecture
instruction set design
0.012001
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation
logic synthesis
0.012001
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001

Methods — techniques the papers use, named apart from their topics

retargetable compilation · 0.0machine description language · 0.0
YearPublicationVenuePosition
2004 A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
abstract
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient ASIP design. In order to circumvent the well-known trade-off between flexibility and code quality in retargetable compilation, we propose a user-guided, semiautomatic methodology that in turn builds on a powerful existing C compiler design platform. Our approach allows to include generated C compilers into the ASIP architecture exploration loop at an early stage, thereby allowing for a more efficient design process and avoiding application/architecture mismatches. We present the corresponding methodology and tool suite and provide experimental data for two real-life embedded processors that prove the feasibility of the approach.
Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren 0001
DATE4
2003 Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models
Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
SCOPES1
2001 A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA
abstract
The development of application specific instruction set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expert knowledge in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be automatically generated including HLL C-compiler, assembler, linker, simulator and debugger frontend. Moreover, synthesizable HDL code can be derived which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for DVB-T acquisition and tracking algorithms designed with the presented methodology are given.
Andreas Hoffmann 0002, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
ICCAD5
2001 A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language
abstract
The development of application-specific instruction-set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend. Moreover, for architecture implementation, synthesizable hardware description language code can be derived, which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for digital video broadcasting terrestrial acquisition and tracking algorithms designed with the presented methodology are given. To show the quality of the generated software development tools, they are compared in speed and functionality with commercially available tools of state-of-the-art digital signal processor and /spl mu/C architectures.
Andreas Hoffmann 0002, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6