Demo Data from EDBT 2026 / reviewers in the wild / expert
Hironori Saito
dblp:22/5904
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Computer networks · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Internet architecture and protocols · 67% Network management and operations · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols
protocol specification |
0.0 | 1 | 1991 | An Integrated Approach to Design of Protocol Specifications Using Protocol Validation and Synthesis · IEEE Trans. Computers 1991 |
Internet architecture and protocols › protocol design
protocol synthesis |
0.0 | 1 | 1991 | An Integrated Approach to Design of Protocol Specifications Using Protocol Validation and Synthesis · IEEE Trans. Computers 1991 |
Network management and operations › protocol verification
protocol validation |
0.0 | 1 | 1991 | An Integrated Approach to Design of Protocol Specifications Using Protocol Validation and Synthesis · IEEE Trans. Computers 1991 |
Methods — techniques the papers use, named apart from their topics
component-based protocol synthesis · 0.0acyclic-expansion-based protocol validation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | Protocol Verification System for SDL Specifications Based on Acyclic Expansion Algorithm and Temporal Logic
Hironori Saito, Toru Hasegawa, Yoshiaki Kakuda |
FORTE | 1 |
| 1991 | An Integrated Approach to Design of Protocol Specifications Using Protocol Validation and SynthesisabstractThe authors propose an integrated approach to protocol specification design and a new method of synthesis of protocol specifications with more than one software module for the approach. In this approach, after designers specify protocols without any restrictions, errors included in the protocol specifications are automatically detected by the acyclic-expansion-based protocol validation and efficiently corrected by the component-based protocol synthesis. In the validation, incomplete specification parts consisting of executable state transition sequences to reach errors in each process are obtained. In the synthesis, the incomplete specification parts are completed by applying certain components which are provided as fundamental parts of correct specifications. The proposed approach has been implemented as an integrated system consisting of CAPE (computer-aided protocol engineering) tools for protocol validation and synthesis. The effectiveness of this approach has been confirmed experimentally. The proposed approach is expected to enhance the productivity of protocol specification design.> Yoshiaki Kakuda, Hironori Saito |
IEEE Trans. Computers | 2 |