A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is presented. The WA technique reduces the problem of writing a "one" through an nMOS pass device, thereby making a single-ended bit line more attractive. Both active power and leakage power can be significantly reduced. Leakage charge can be pooled to help precharge bit lines. Cell area and performance are competitive with traditional SRAM cell area and performance

Our objective was to integrate an effective channel routing algorithm with the Chip Design Language (CDL) algorithmic layout tool. CDL uses technology targetable layout techniques, so that the output of the routing algorithm can easily be ported to different technologies. We introduce the technology independent features of CDL and describe how a greedy router can be interfaced to it. Specific features of interest include mapping from the grid based router to the gridless CDL environment, and the automatic insertion of CDL feed-through cells in multi-channel applications.

The design of a versatile CMOS semi-static true singlephase clock flip-flop family is presented. It naturally supports multiple, multiplexed, inputs. Asynchronous Set/Reset are easily implemented. Switching power is lower than for some other semi-static flip-flop techniques.

The asynchronous transfer mode (ATM) reassembly algorithm for adaptation layer five is broken down into concurrent tasks for efficient VLSI implementation. VHDL and HSPICE simulations show that the proposed reassembly chip architecture will function with ATM line rates up to 700 Mb/s. The architecture is based upon three embedded lightweight processors, a variety of supporting circuitry, and a peripheral component interface (PCI) bus host interface. An important architectural feature is the use of a paged memory management system for the reconstruction of variable length messages.

Power saving techniques for CMOS programmable logic arrays (PLAs) are discussed. Two new techniques are introduced, an AND-plane pulse generator, and wired-OR CMOS. Power reduction in excess of 75% over pseudo-NMOS techniques and 50% over some clocked PLA techniques is possible.

New single- and multiprocessor models for ray tracing are presented. Important features are (1) the use of custom VLSI building blocks, (2) the use of a modified hierarchical data-structure-based ray tracing algorithm with three disjoint data sets, and (3) scene access through adaptive information broadcasting. A modular design is presented that permits incremental performance enhancement up to two orders of magnitude over conventional minicomputers or workstations. Ray tracing is a surprisingly good application for a shared bus architecture because of the computational complexity of intersecting light rays with graphics objects.

A canonical internal form for APL is derived.A directly executable language (ADEL) follows DEL principles first developed by Flynn and Hoevel.APL usage statistics are reported and used to help determine an efficient encoding strategy.Two execution models are discussed.The models show that for a vector-oriented host machine, the use of expression temporaries may be ~nore efficient, not less efficient as expected for a scalar-oriented host.