This paper proposes an energy- and area-efficient sound localization neural network mimicking the auditory brainstem cognitive function. By adopting the bio-plausible Jeffress model, the proposed neural network locates the sound based on the interaural time difference (ITD) in an energy- and hardware-efficient manner. The proposed network modifies the original structure of the Jeffress model having a pair of long axon lines to provide performance gain. It can reduce power consumption and area by using a single axon line. It can further improve efficiency in terms of power and area by shortening the length of the axon line for pulse propagation. Since only the leading pulse is allowed to propagate through the shortened single axon delay line, the number of delay elements and corresponding network components are reduced. Moreover, it can accurately detect the location of the sound source thanks to the axon line composed of synchronized delay elements. A further reduction of the power consumption is achieved by eliminating redundant pulse propagation through the axon line after the output neuron fires. The proposed sound localization neural network was fabricated in a 28-nm CMOS process. The performance evaluation results indicate that the proposed sound localization neural network can detect the location of a sound source with a one-degree resolution at a given robot head size of 3.0125 cm, regardless of process corners. It also indicates that the network achieves up to 86.6% and 97.2% energy and area reduction from conventional sound localization networks, operating at 0.305-V supply voltage.

While contrastive learning has been the mainstream in self-supervised learning, negative sampling for learning is a challenging issue. To resolve this problem, recent studies instead used a pair of augmented images generated from each image as positive samples and trained models by maximizing the similarity between representation vectors. However, training models using positive samples may not be enough to let the models learn rich representations because these methods cannot consider the information from different images. To address the issue, we propose a learning method that uses clustered positive samples from different images to allow the network to learn better. As the first step, our method learns invariance representations from augmented images. Next, the resulting representation vectors are clustered to learn rich representations. According to our evaluation, it was found that our method achieved better performance than other models using a clustering method from scratch. Moreover, in downstream tasks, our model achieved a higher classification accuracy than Barlow Twins under the same experimental setting. Therefore, adding the distance information on the class centroid to the loss function of self-supervised learning can improve performance by exploiting rich representations in the data.

In this paper, a high-speed low-power CMOS synchronous up/down counter with a novel compact toggle flip-flop is proposed to achieve energy- and area-efficient speed enhancement. It adopts a high-speed local clock generation based on a single Manchester carry chain to improve counting speed. The counter embeds clock gating in the local clock generation to eliminate redundant power consumption. A compact toggle flip-flop is incorporated for device count and power reduction. Both the up- and down-counting capabilities are supported. A 16-bit proposed counter was fabricated in a 28-nm CMOS process. Performance evaluation results indicate that the proposed counters can provide up to 55% speed improvement as compared to conventional designs. It also indicates that up to 28% performance gain is obtained in terms of power-delay product compared to conventional clock-gated CMOS counters.

This paper proposes CMOS synapse and neuron for use in spiking neural networks to perform cognitive functions in a bio-inspired manner. The proposed synapse can trace the eligibility of the timing relationship between pre- and post-synaptic spikes, supporting a bio-plausible local learning rule called the spike timing-dependent plasticity (STDP) in an energy- and area-efficient manner. The proposed neuron can support neural functions such as synaptic current integration, threshold-based firing, neuronal leaking, membrane potential resetting, and adjustable refractory period with improved energy and area efficiency. The STDP curve shape of the synapse and the firing rate of the neuron can be adjusted as desired. Their variability due to process, voltage, and temperature (PVT) variations can also be minimized. The proposed CMOS neuron and synapse circuits were designed in a 28-nm CMOS process. The performance evaluation results indicate that the proposed synapse reduces energy consumption and area by up to 94% and 43% compared to conventional CMOS synapses. They also indicate that the proposed neuron achieves energy and area reductions of 37% and 23%, respectively, compared to conventional CMOS neurons. An associative neural network composed of the proposed neuron and synapse was designed to verify that they together work well for performing a cognitive function of associative learning and inferencing.

We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm2, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes.

We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell's supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the VDDlevel for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL precharging level during the write and the hold mode, and are connected to true supply levels only during the read operation. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is 2.47× the size of 6T with β = 2, provides 2.3× read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and (ION/IOFF)is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved.

A conditional-boosting flip-flop is proposed for ultralow-voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage boosting to provide low latency with reduced performance variability in the near-threshold voltage region. It also adopts conditional capture to minimize the switching power consumption by eliminating redundant boosting operations. Experimental results in a 65-nm CMOS process indicated that the proposed flip-flop provided up to 72% lower latency with 75% less performance variability due to process variation, and up to 67% improved energy-delay product at 25% switching activity compared with conventional precharged differential flip-flops.

A CMOS charge pump adopting dual charge transfer switches and a transfer blocking technique is presented. Using these techniques, the proposed charge pump eliminates reversion loss and improves driving capability. A test chip is designed in a 46-nm CMOS process, whose evaluation results show that, with no loading current, the proposed CMOS charge pump achieves 9.1% improvement of voltage conversion ratio. They also show that the proposed charge pump provides up to 132% improvement on current driving capability, as compared with the conventional CMOS charge pumps.

In this paper, a low-power embedded pseudo-SRAM adopting novel auto-adjusted self-refresh control scheme has been designed. The proposed self-refresh control scheme automatically extends the self-refresh period by monitoring the number of failed cells using error correction code (ECC). The scheme can provide a substantial reduction of data-retention power consumption by choosing an optimal self-refresh period regardless of process, voltage, and temperature (PVT) variations. A 4-Mb embedded pseudo-SRAM designed in a 45-nm embedded DRAM technology providing 1.1-V 166-MHz random cycle operation achieves 57-uW data retention power consumption at room temperature.

In this paper, presetting pulse-based flip-flop (PSPFF) is proposed. The flip-flop briefly presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. This presetting operation allows the proposed flip- flop to be faster and more clock-skew tolerant than conventional pulse-based flip-flops. Comparison results using a 80-nm CMOS process technology indicate that PSPFF has 22% improvement on clock-skew tolerance, 20% decrease of data-to-output delay, 22% reduction of power-delay product, and 21% reduction of layout area, as compared to PCSPFF.

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm2with under 1uW power consumption for providing 0.7°c effective resolution at 1 sample/sec processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.

This paper proposes PVT-invariant single-to-differential signal converter (SDQ applicable to the output circuitry of high-speed DDR SDRAM. The proposed SDC generates PVT-invariant differential-output sampling clock using a phase interpolation technique and a symmetric structure, and improves the aperture window of output data in source synchronous DDR SDRAM. The proposed SDC was simulated using 1.8-V 80-nm DRAM technology. The comparison result indicates that the differential clocks generated by the proposed SDC achieve 80.6% reduction of skew, 76.6% reduction of duty-cycle distortion, 61.7% of reduction of delay variation, and 8.5% reduction of maximum current for a given process, voltage, and temperature (PVT) variations, as compared to conventional SDCs. The I/O interface of a source-synchronous DDR SDRAM designed using the proposed SDC, which is operating at 1.0-Gbps/pin data rate has aperture window increased by 15.3% and ISI improved by 67.7% in comparison to conventional I/O interface.

This paper presents Needle Auto Calibration (NAC) probing technique to measure the electrical characteristics of Probecard for wafer-level test. Probecard needle alignment and probing tasks, which are generally known to be hard and time-consuming, can be done easily through automatic Probecard aligning function of NAC. The inaccuracy problem during measurements by NAC probing due to difficulties of calibration is compensated by adapter characterization and de-embedding techniques. According to our experimental results, the inaccuracies of group delay, insertion loss and phase characteristic are decreased from 30.4% to 2.71%, from 1.75% to 0.53%, and from 35.2% to 1.32%, respectively.

In this paper, a novel CMOS differential logic family, called data-dependent evaluating latched CMOS logic (DELL), is proposed for use in low-power VLSI. The proposed logic family discharges internal precharge nodes on demand, and thus, statistically reduces the power consumption during logic operation. The self-resetting version of the logic family can also boost the operating clock frequency by performing precharge operation as early as possible. It has the additional advantage of clock power reduction by reducing the clock load. The proposed logic family was designed using 0.35 /spl mu/m CMOS process technology. The comparison results show that the proposed logic family consumes less power than the conventional logic family for the switching activity smaller than 0.7, and achieves a power saving of up to 75%. The improvement of power, delay product is also about 34%.