Since the problem of power integrity has become a critical issue that limits design performance, obtaining the supply current waveforms at early design stages is essential to achieve efficient reduction of supply noise. Therefore, a high-level current macro model is proposed by Bodapati and Najm for logic blocks to provide fast current waveform estimation at register-transfer level (RTL). However, due to the different arrival time of internal signals, modeling the supply current of the entire logic block accurately as specific fixed templates is difficult. This paper thus proposes a levelized high-level current model for logic blocks. By merging gates with similar arrival time as a super-gate and recording its current waveforms separately, obtaining more accurate supply current waveforms is possible by using a unified model, even for multipeak cases. This paper also proposes a frequency-domain waveform transformation method to consider the effects of nonideal supply resistance on the supply current waveform. As shown in the experimental results, the peak error and waveform correlation of the proposed current model are significantly improved compared to the results of the single-stage current model. Using accurate supply current waveforms can also help obtain precise IR-drop estimation in RTL simulations for early system evaluation.

In the nanometer era, IR-drop has become one of the critical issues in current VLSI designs. Although checking this problem earlier can speed up the analysis, not many tools are available now due to the limited design information. Most existing approaches at gate level require additional characterization to consider the effects of different resistances on supply lines. Therefore, an analytical method is proposed to estimate the IR-drop values without extra information. After modifying the data stored in standard libraries (.lib) and the events stored in activity files (.vcd), using the previous method can also obtain accurate supply current waveforms and IR-drop values for any given supply resistance, as demonstrated by the experiments on several benchmark circuits.

In nanometer era, the power integrity problem has become one of the critical issues. Although checking this problem at higher level can speedup the analysis, not so many tools are available now due to the limited design information at high levels. Most existing approaches at gate level require extra information of the cell library, which may require extra characterization efforts while migrating to new cell libraries. Therefore, we propose an accurate approach to estimate the supply current waveform of sequential circuits at gate level using existing library information only. The experimental results have shown that the estimation errors of our approach are less than 9% compared to HSPICE results, which are better than the rough estimation in [8].