This paper deals with the design of coding/modulation and demodulation/decoding schemes for single- or multiple-antenna systems with focus on fast-fading channels, where channel state information (CSI) is not available at the transmitter and the receiver. We explore two possible solutions for this channel with increasing degree of sophistication. The first one utilizes pilots at the transmitter and a simple and explicit noniterative channel estimation algorithm at the receiver. We show that this pilot-assisted system is exactly equivalent, in terms of performance analysis and design, to an appropriately "degraded" system having perfect CSI at the receiver. The second scheme utilizes pilots and a family of well-justified and simple suboptimal iterative detection/estimation algorithms. It is shown that when turbo-like codes are considered in conjunction with this pilot-assisted transmission scheme and the proposed receiver algorithm, the unitary constellations investigated in the literature are inferior to simple pilot-assisted constellations in both complexity and performance. Specific instances of the proposed systems (that use optimized irregular low-density parity-check outer codes) are designed. The design examples provided show that the proposed systems can achieve a good tradeoff between complexity and performance and can be used to bridge the gap between the high complexity/high-performance optimal scheme and low-complexity/mediocre performance noniterative estimation/coherent detection scheme.

The implementation of a superscalar, speculative execution SPARC-V9 microprocessor incorporating Restricted Data Flow principles required many design trade-offs. Consideration was given to both performance and cost. Performance is largely a function of cycle time and instructions executed per cycle while cost is primarily a function of die area. Here we describe our Restricted Data Flow implementation and the means with which we arrived at its configuration. Future semiconductor technology advances will allow these trade-offs to be relaxed and higher performance Restricted Data Flow machines to be built.