Demo Data from EDBT 2026 / reviewers in the wild / expert
Oliver Mischke
dblp:22/8341
· DBLP profile ↗
7ranked-venue papers
1as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 6 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
5 papers |
Hardware security and side channels · 87% Cryptographic primitives and cryptanalysis · 13% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
side-channel attack |
0.4 | 3 | 2013 | One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores · IEEE Trans. Computers 2013 On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting · CHES 2011 Correlation-Enhanced Power Analysis Collision Attack · CHES 2010 |
Hardware security and side channels
side-channel countermeasures |
0.3 | 2 | 2013 | On the Simplicity of Converting Leakages from Multivariate to Univariate - (Case Study of a Glitch-Resistant Masking Scheme) · CHES 2013 How Far Should Theory Be from Practice? - Evaluation of a Countermeasure · CHES 2012 |
Hardware security and side channels › side-channel countermeasures
masking |
0.2 | 1 | 2013 | On the Simplicity of Converting Leakages from Multivariate to Univariate - (Case Study of a Glitch-Resistant Masking Scheme) · CHES 2013 |
Hardware security and side channels
side-channel leakage |
0.2 | 1 | 2013 | On the Simplicity of Converting Leakages from Multivariate to Univariate - (Case Study of a Glitch-Resistant Masking Scheme) · CHES 2013 |
Hardware security and side channels › side-channel attack
timing side channel |
0.2 | 1 | 2013 | One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores · IEEE Trans. Computers 2013 |
Cryptographic primitives and cryptanalysis › hash function cryptanalysis
collision attack |
0.1 | 1 | 2011 | On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting · CHES 2011 |
Cryptographic primitives and cryptanalysis
block cipher cryptanalysis |
0.0 | 1 | 2013 | One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores · IEEE Trans. Computers 2013 |
Methods — techniques the papers use, named apart from their topics
fault sensitivity analysis · 0.2correlation collision attack · 0.2collision timing attack · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Fault Sensitivity Analysis Meets Zero-Value AttackabstractPrevious works have shown that the combinatorial path delay of a cryptographic function, e.g., The AES S-box, depends on its input value. Since the relation between critical path delay and input value seems to be relatively random and highly dependent on the routing of the circuit, up to now only template or some collision attacks could reliably extract the used secret key of implementations not protected against fault attacks. Here we present a new attack which is based on the fact that, because of the zero-to-zero mapping of the AES Sbox inversion circuit, the critical path when processing the zero input is notably shorter than for all other inputs. Applying the attack to an AES design protected by an state-of-the-art fault detection scheme, we are able to fully recover the secret key in less than eight hours. Note that we neither require a known key measurement step (template case) nor a high similarity between different S-box instances (collision case). The only information gathered from the device is whether a fault occurred when processing a chosen plaintext. Oliver Mischke, Amir Moradi 0001, Tim Güneysu |
FDTC | 1 |
| 2013 | On the Simplicity of Converting Leakages from Multivariate to Univariate - (Case Study of a Glitch-Resistant Masking Scheme)
Amir Moradi 0001, Oliver Mischke |
CHES | 2 |
| 2013 | Comprehensive Evaluation of AES Dual Ciphers as a Side-Channel Countermeasure
Amir Moradi 0001, Oliver Mischke |
ICICS | 2 |
| 2013 | One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC CoresabstractWhen complex functions, for example, substitution boxes of block ciphers, are realized in hardware, timing attributes of the underlying combinational circuit depend on the input/output changes of the function. These characteristics can be exploited by the help of a relatively new scheme called fault sensitivity analysis. A collision timing attack which exploits the data-dependent timing characteristics of combinational circuits is demonstrated in this paper. The attack is based on an also recently published correlation collision attack, which avoids the need for a hypothetical timing model for the underlying combinational circuit to recover the secret materials. The target platforms of our proposed attack are 14 AES ASIC cores of the SASEBO LSI chips in three different process technologies, 13 nm, 90 nm, and 65 nm. Successfully breaking all cores including the DPA-protected and fault attack protected cores indicates the strength of the attack. Amir Moradi 0001, Oliver Mischke, Christof Paar |
IEEE Trans. Computers | 2 |
| 2012 | How Far Should Theory Be from Practice? - Evaluation of a Countermeasure
Amir Moradi 0001, Oliver Mischke |
CHES | 2 |
| 2011 | On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting
Amir Moradi 0001, Oliver Mischke, Christof Paar, Yang Li 0001, Kazuo Ohta, Kazuo Sakiyama |
CHES | 2 |
| 2010 | Correlation-Enhanced Power Analysis Collision Attack
Amir Moradi 0001, Oliver Mischke, Thomas Eisenbarth 0001 |
CHES | 2 |