When we analyze the scaling factors of the recent technology nodes, we come to the conclusion that the geometrical scaling scenario has been replaced by the electrical scaling and hence the electrical characterization of these really challenging technologies becomes an absolute must. However, the extremely small process windows, and the 3-dimensional nature of the FinFET devices and the complicated interconnect schemes, make this characterization very difficult. Systematic failure modes and their dependence on the layout patterns are extremely complex and almost impossible to detect in-line. Moreover, soft failures become much more prevalent due to process marginalities and present not only yield but also reliability hazards. Hence, the new fault models must be created that take into account layout patterns and layout-process interactions to allow for more efficient testing and reliability risk screening. This talk will present novel approaches to electrical characterization of the dominant failure modes, its impact on the test generation and execution, and the need for tracking this information all the way from the front end process to the test and assembly stages of IC manufacturing.

Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTCO) for standard cell logic. In our holistic DTCO we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTCO in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.

In this paper, we propose a methodology based on unsupervised learning for automatic clustering of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number of features. Next, we apply an unsupervised hierarchical clustering algorithm to divide wafers into a few clusters where all wafers within the same cluster are similar. Finally, we develop a modified L-method to determine the appropriate number of clusters from the hierarchical clustering result. The accuracy of the proposed methodology is demonstrated by several industrial data sets of silicon measurements.

In this paper, we propose a new technique to achieve accurate decomposition of process variation by efficiently performing spatial pattern analysis. We demonstrate that the spatially correlated systematic variation can be accurately represented by the linear combination of a small number of templates. Based on this observation, an efficient sparse regression algorithm is developed to accurately extract the most adequate templates to represent spatially correlated variation. In addition, a robust sparse regression algorithm is proposed to automatically remove measurement outliers. We further develop a fast numerical algorithm that may reduce the computational time by several orders of magnitude over the traditional direct implementation. Our experimental results based on both synthetic and silicon data demonstrate that the proposed sparse regression technique can capture spatially correlated variation patterns with high accuracy and efficiency.

For decades, Moore's law transistor cost scaling created a vibrant ecosystem of foundries, fabless design houses, IDMs, and suppliers. Each of these parties shared in the abundant economic benefits of the transistor cost scaling enabled by Moore's law. This led to specialization within each layer and vertical segment of the supply chain wherein rigid technical interfaces allowed unidimensional technology trajectories to thrive. As we approach the challenges of achieving economic scaling at 22nm and beyond, we are confronted with a new set of challenges that will require tighter integration along historically rigid interfaces. This environment sets the stage for the pendulum to swing toward technologies that take advantage of tighter coupling between layout architectures and process capabilities, and between process control needs and product sensitivities. Taking the next step in Moore's law with the application of smarter and more efficient circuit, layout, and lithography co-design techniques that can provide high density and increased yields at a sustainable cost. The key enabler of this methodology is the creation of a regular design fabric onto which one can efficiently map the selected templates using a limited number of printability-friendly layout patterns. The co-optimization of circuit, layout, and process is achieved by co-developing circuit functions, layout pattern library and lithography solutions. This solution replaces design rules for logic with a rigorously characterized set of layout Templates. We will demonstrate that this methodology will enable future technology nodes that utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choice of regular design fabrics and their implications on design metrics, yields and cost; show that the selection of circuit topologies can be mapped efficiently to the choice of regular design fabric, and compare lithography solutions such as double patterning (DPT), direct write multi-e-beam (MEBM) and interference lithography (IL) for the 22nm technology node and beyond.

Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with the main emphasis on design and architecture solutions. Specifically, this panel will discuss:• Would new architectures mitigate variability in 22nm and beyond?• Could design regularity effectively mitigate variability?• What design techniques can be used to minimize variability 'on-the-fly'?• What new techniques can be used for memories, register arrays and flip-flops?

The financial backbone of the semiconductor industry is based on doubling the functional density of integrated circuits every two years at fixed wafer costs and die yields. The increasing demands for 'computational' rather than 'physical' lithography to achieve the aggressive density targets, along with the complex device-engineering solutions needed to maintain the power density objectives, have caused a rapid escalation in systematic yield limiters that threaten scaling. Specifically, the traditional contract between design and manufacturing based solely on design rules is no longer sufficient to guarantee functional silicon and instead requires a convoluted set of restrictions that force complex modifications to the already costly design flows. In this paper, we claim that a far superior result can be achieved by moving the design-to-manufacturing interface from design rules to a higher level of abstraction based on a defined set of pre-characterized layout templates. We will demonstrate how this methodology can simplify optical proximity correction and lithography processes for sub-32 nm technology nodes, along with various digital block design examples for synthesized intellectual property (IP) cores. Furthermore, with a cost-per-good-die analysis we will show that this methodology will extend economical scaling to sub-32 nm technology nodes.

Achieving the required time-to-market with economically acceptable yield levels and maintaining them in volume production has become a daunting task for the advanced technology nodes. These difficulties are primarily attributable to the increase in process variability that is incurred while aggressively scaling technology nodes which are based on the same fundamental device architectures and process solutions. The introduction of a Metal Gate/High-K (MGHK) stack at the 32/28nm technology node will help in addressing the random variations due to random dopant fluctuations (RDF), but its benefit will be exhausted after a single process generation [3]. As a result, for the 22/20nm technology nodes, the only hope to limit RDF will be to adopt novel device architecture, such as FinFET and Ultra Thin Body or Fully Depleted SOI, that would reduce the dopant concentration in the channel.

Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. "Surgeons" suggest a GDSII-centered approach, potentially invasive, while "family doctors" recommend a more pervasive approach, starting from RTL. As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks. This panel examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such "hazardous" conditions as state-of-the-art technologies. However, as always, "the devil is in the details", and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the "health hazards". We are looking forward to an exciting discussion that will challenge our esteemed panelists

Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns [6,7] can provide significant advantages in terms of manufacturability and design cost [2]. Various forms of gate and logic arrays have been recently proposed that can offer such pattern regularity to reduce design risk and costs [2,4,9,11,12]. In this paper, we propose a full-mask-set design methodology which provides the same physical design coherence as a configurable array, but with area and other design benefits comparable to standard cell ASICs. This methodology is based on a set of simple logic primitives that are mapped to a set of logic bricks that are defined by a restrictive set of RET(Resolution Enhancement Technique)-friendly geometry patterns. We propose a design methodology to explore trade-offs between the number of bricks and associated level of configurability versus the required silicon area. Results are shown to compare a design implemented with a small number of regular bricks to an implementation based on a full standard cell library in a 90nm CMOS technology.

Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The Non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, we present an efficient block-based statistical timing analysis approach with linear complexity with respect to the circuit size, which can accurately predict Non-Gaussian delay distributions from realistic nonlinear gate and interconnect delay models. This approach accounts for all correlations, from manufacturing process dependence, to re-convergent circuit paths to produce more accurate statistical timing predictions. With this approach, circuit designers can have increased confidence in the variation estimates, at a low additional computation cost.

Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projection-based extraction approach, PROBE, to efficiently create quadratic response surface models and capture both inter-die and intra-die variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12/spl times/ speedup compared with the traditional methods.

Critical path analysis is always an important task in timing verification. For todays nanometer IC technologies, process variations have a significant impact on circuit performance. The variability can change the criticality of long paths (Gattiker et al., 2002). Therefore, statistical approaches should be incorporated in critical path analysis. In this paper, we present two novel techniques that can efficiently evaluate path criticality under statistical non-linear delay models. They are integrated into a block-based statistical timing tool with the capability of handling arbitrary correlations from manufacturing process dependence and also path sharing. Experiments on ISCAS85 benchmarks as well as industrial circuits prove both accuracy and efficiency of these techniques.

No abstract available.

In an effort to control the parameter variations and systematic yield problems that threaten the affordability of application-specific ICs, new forms of design regularity and structure have been proposed. For example, there has been speculation [6] that regular logic fabrics [1] based on regular geometry patterns [2] can offer tighter control of variations and greater control of systematic manufacturing failures. In this paper we describe a routing framework that accommodates arbitrary descriptions of regular and structured routing architectures. We further propose new regular routing architectures and explore the various performance vs. manufacturability trade-offs. Results demonstrate that a more regular, restricted routing architecture can provide a substantial advantage in terms of manufacturability and predictability while incurring a moderate performance penalty.

Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The AUTHORs, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the problems and the solutions for achieving manufacturability and yield goals.

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

In this era of Deep Sub-Micron (DSM) technologies, interconnects are becoming increasingly important as their effects strongly impact the integrated circuit (IC) functionality and performance. Moreover, logic block size is no longer determined exclusively by total cell area, and is often limited by wiring resources, yet synthesis optimization objectives are focused on minimizing the number and size of library cells. Methodologies that incorporate congestion within the logic synthesis have been proposed in the past. However, in [15] and [16] it was demonstrated that predicting the true congestion prior to layout is not possible, since different layout regions can have very different routing demands, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the assigned die size. In these works, congestion minimization efforts at the synthesis level are controlled by means of a global weighting factor in the technology mapping cost function. Nevertheless, due to the lack of accurate congestion models, during logic synthesis it is not possible to estimate a priori which values of the congestion minimization factor will yield a congestion-free synthesized netlist. In this paper, we derive practical bounds, which limit the search space for an optimal congestion minimization factor that produces a routable netlist within fixed floorplan constraints. Although we believe that a top-down single-pass congestion-aware logic synthesis is not going to work in general, the bounds obtained in this work can be used in a practical and robust congestion minimization methodology, which can be implemented into any commercial design flow.

In this era of deep submicrometer technologies, interconnects are becoming increasingly important as their effects strongly impact the integrated circuit (IC) functionality and performance. Moreover, logic block size is no longer determined exclusively by total cell area and is often limited by wiring area. However, synthesis optimization objectives are focused on minimizing the number and size of library cells. Methodologies that incorporate congestion within the logic synthesis objective function have been proposed in the past. Nevertheless, we will demonstrate that predicting the true congestion prior to layout is not possible, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the fixed die size. In this paper, we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the technology-dependent synthesis cost function and then applies incremental localized unmapping and remapping on layout congested areas. This complete approach addresses the problem that one global factor is not suited for all layout regions of the design, which might have very different routing demands. Most importantly, through the application of this methodology to industrial examples, we will show that any attempt at a purely top-down single-pass congestion-aware technology mapping is merely wishful thinking.

In this era of Deep Sub-Micron (DSM) technologies, the impact of interconnects is becoming increasingly important as it relates to integrated circuit (IC) functionality and performance. In the traditional top-down IC design flow, interconnect effects are first taken into account during logic synthesis by way of wireload models. However, for technologies of 0.25 /spl mu/m and below, the wiring capacitance dominates the gate capacitance and the delay estimation based on fanout and design legacy statistics can be highly inaccurate. In addition, logic block size is no longer dictated solely by total cell area, and is often limited by wiring area resources. For these reasons, wiring congestion is an extremely important design factor, and should be taken into consideration at the earliest possible stages of the design flow. In this paper we propose a novel methodology to incorporate congestion minimization within logic synthesis, and present results for industrial circuits that validate our approach.

Traditionally, interconnect effects are taken into account during logic synthesis via wireload models, but their ineffectiveness for DSM technologies has been demonstrated and various physical synthesis approaches have been spawned to address the problem. Of particular interest is that logic block size is no longer dictated exclusively by total cell area, yet synthesis optimization objectives are aimed specifically at minimizing the number and size of cells. Methodologies that incorporate congestion within the logic synthesis objective function have been proposed in [9][10][11] and [15]; however, as we will demonstrate, predicting the true congestion prior to layout is not possible, and the efficacy of any approach can only be evaluated after routing is completed within the fixed die size. In this paper we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the cost function [15], and then applies incremental localized unmapping and remapping on congested areas. This complete approach addresses the problem that one global factor is not ideally suited for all regions of the designs. Most importantly, through the application of this methodology to industrial examples we will show that any attempt at a purely top-down single-pass congestion-aware technology mapping is merely wishful thinking.

Published research on path delay fault (PDF) testing has largely focused on the PDF classification and test-vector generation problems. Little attention has been paid to the diagnosis of delay faults and in defining realistic metrics for delay-fault coverage, We present a statistical diagnosis framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay-fault tests. Under a model where distributed fabrication-process perturbations contribute to the occurrence of delay faults, we also find the associated likely fabrication-process parameter deviations from their nominal values as part of the diagnosis framework. We present results of experiments performed on some International Symposium on Circuits and Systems 1989 (ISCAS'89) benchmark circuits and also relate the slack of a path segment to its probability of contributing to the circuit failure. We also quantify the diagnosability of a PDF for a test and develop a methodology based on our statistical diagnosis framework to determine the diagnosability of each PDF detected by a given test set. We apply this approach to find the diagnosability of robust PDFs for the ISCAS'89 benchmark circuits. Furthermore, we propose a new and realistic definition of delay-fault coverage based on the percentage of fabricated faulty chips that can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay-fault sizes caused by the chip manufacturing process as opposed to previously defined metrics that have been based primarily on the percentage of faults tested. We present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of PDFs caused by distributed fabrication-process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between PDF coverage estimates for robust test sets obtained using our realistic definition and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.

No abstract available.

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.

Design of reliable chips with high yield is an extremely challenging task in UDSM technologies. Time to market pressures, which often limit the necessary verification before tape-out, typically are manifested as ramp-to-production problems on “good” designs either in the manufacturing process or in the field. Burn-in process, a reactive measure to ship reliable chips, is not effective for high volume designs. Another cause for concern is hidden failures that go undetected due to incompleteness of test vectors.

Summary form only given. This tutorial presents the requirements for the design-manufacturing interface in the upcoming generations of ULSI technologies. We start by presenting an overview of trends in the semiconductor industry: accelerated roadmap which leads to further miniaturization, the increasing role of manufacturing fluctuations, shrinking time to market, product complexity (including SOC) and the overall disaggregation of semiconductor industry (emergence of fabless companies and increasing role of foundries in manufacturing). Then we discuss the current, isolated approach to process development, product design and volume manufacturing. We conclude the tutorial by discussing the technical and organizational challenges that must be overcome to successfully implement this new design-manufacturing interface.

Computer-aided design (CAD) techniques are absolutely essential to harness the ever-increasing complexity of the microsystem design. Similarly, the technology CAD (TCAD) tools played a key role in the development of new technology generations. Although there is a common belief that the TCAD tools have been trailing the technology development, the situation has been changing very significantly especially over the last decade. For the deep submicrometer (DSM) devices, these tools provide a better insight than any measurement techniques and they have become indispensable in the new device creation. Moreover, these tools after calibration to a relatively small number of experiments, exhibit very impressive predictive power, which is utilized to speed up the technology integration and transfer to volume manufacturing. This results in very manufacturable high-yielding products that can be ramped up much faster than in the past decade, which is absolutely necessary given the huge costs of integrated circuit fabrication lines, short product lifecycles and penalties for being late to the market place. In this paper, we present our perspective on the semiconductor technology development, and highlight the rapid growth of TCAD and its strategic use in the semiconductor industry.

Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We prove that the maximum primitive PDF delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. From this result, we devise a method to perform timing analysis based on primitive PDF identification which delinks functional analysis from delay computation. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re-identified due to component delay speedup (e.g., post-layout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.

Article Model order-reduction of RC(L) interconnect including variational analysis Share on Authors: Ying Liu Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PAView Profile , Lawrence T. Pileggi Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PAView Profile , Andrzej J. Strojwas Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 201–206https://doi.org/10.1145/309847.309914Online:01 June 1999Publication History 44citation390DownloadsMetricsTotal Citations44Total Downloads390Last 12 Months14Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC's which suggest that the diversity of patterns does not significantly increase with increasing chip size.

Recursive convolution provides an exact solution for interfacing reduced-order frequency domain representations with discrete time domain models of piecewise linear voltage waveforms. The state-space method is more efficient, but not exact, and can sometimes produce large time domain errors. This paper presents a new algorithm, ftd (frequency to time domain), for incorporating linear frequency domain macro-models into time domain simulators. ftd provides accuracy equivalent to recursive convolution with efficiency that is superior to the state-space methods.

We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the information stored within the pattern and position of the pattern instance. We also show preliminary results of analysis of the state-of-the-art ICs which suggest that the diversity of patterns does not significantly increase with the increase of chip size.

We present a novel timing analysis mechanism which is based on identifying primitive path delay faults (primitive PDFs) in a circuit. We show that this approach gives the exact maximum delay of the circuit under the floating mode of operation assumption. Our timing analysis approach provides a framework where component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects can be handled very accurately. Under these effects, timing analysis using previously reported floating mode timing analyzers, e.g., viability, TrueD-F etc., is very pessimistic. Our timing analysis approach based on primitive PDF identification is also more efficient than conventional floating mode path sensitization analysis mechanisms in situations where critical paths need to be re-identified due to component delay speedup (e.g., postlayout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.

In this paper, we propose a new and realistic definition of delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay fault sizes caused by fabrication process effects, as opposed to previously defined metrics which have been based primarily on the percentage of faults tested. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of path delay faults caused by distributed fabrication process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between distributed path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.

This paper discusses manufacturabilty of state-of-the-art low power technologies.We report the results on two generations of bulk CMOS technologies, triple-well CMOS and Thin Film Silicon on Insulator (TFSOI) technologies.We present technology capabilities for several values of supply voltage and address the issue of performance scaling with the supply voltage reduction.Then we focus on the statistical characterization of these technologies and discuss both interchip and intrachip variations.Finally, we present the digital and analog designer perspectives on the low power IC operation.

Published research on delay fault testing has largely focused on generating a minimal set of test vector pairs to detect as many delay faults in a circuit as possible. Little regard has been paid to the diagnosability of delay faults in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. In an earlier work [1996] we presented a framework to detect which paths are likely to have caused a chip failure for a set of delay fault tests, and to find the associated likely fabrication process parameter variations. Here, we quantify the diagnosability of a path delay fault for a test, and develop a methodology based on the diagnosis framework presented earlier to determine the diagnosability of each path delay fault detected by a given test set. Furthermore, we apply this approach to find the diagnosability of robust path delay faults for the ISCAS'89 benchmark circuits.

Previous research in the field of path delay fault test generation has concentrated on finding tests which test paths regardless of component delay values. Coverage of such tests on benchmark circuits has been shown to be poor so we present a mechanism wherein path delay fault tests are found under the assumption of component delay variations resulting from fabrication process fluctuations. Component delay fault models are built which incorporate fabrication process effects represented in terms of basic process parameter variations. We use a sensitization approach based on signal stabilizing times to get conditions on primary inputs and path delays for which a delay fault is produced at the circuit outputs. A minimal test set is then extracted from these conditions. Results for the ISCAS'89 and Logic synthesis'91 benchmark circuits indicate the feasibility of this approach.

This paper presents a new approach to 3-dimensional thermal simulation of arbitrary electronic systems.This approach is based on the combination of numerical (finite elements and finite differences) and analytical (Fourier series) techniques which are very general and extremely efficient.Complex electronic systems (monolithic IC's, multichip modules, including their packaging) can be analyzed in minutes on PC's to produce a detailed temperature distributions within the system structure.The software system, MON-STR, has been developed and applied to several industrial examples.The results of this analysis are directly entered to the circuit simulator, HSPICE, as the actual temperature for each circuit element and thus an integrated electro-thermal simulation is performed.

In this paper, a stochastic interpolation model (SIM) scheme is proposed to approximate circuit performances for statistical circuit design purpose. First, a parameter estimation technique for SIM construction is presented. Next, a sequential sampling strategy based on variance analysis is described to efficiently fit SIM with the least amount of sample data. Finally, the coefficient of variance is introduced as a new criterion for approximation accuracy check. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.>

An approach to computing the time response of an arbitrary 3-D interconnect structure based on asymptotic waveform evaluation (AWE) is introduced. It has been implemented in a software tool called 3DAWE. To facilitate the application of AWE to a 3D RC mesh network model, the AWE formulation is rederived based on a nodal analysis approach. The ICCG matrix solver has been successfully applied in 3DAWE. It is shown that the typical transient response of a reasonably large 3D RC network can be obtained within a few minutes on a 15-MIPS computer using this program.>

The chip database (CDB) and the hierarchical chip database (HCDB) and their uses in a wafer representation server are described. The server provides data types and methods for hierarchically representing the three-dimensional geometry and fields of a semiconductor wafer during process, device, and yield simulation. The basic database data types and the general attribute mechanism have been used to create database extensions. These extensions implement operations frequently used by process and device simulation models. The combination of the databases and extensions forms a CDB/HCDG server that greatly reduces the effort required to create new statistical process, device, and yield simulation models. Examples of using the server to implement new models are described. Performance data demonstrate that the server is fast enough for use by analytical models during statistical simulation of macrocells, and is able to meet the representation needs of numerical simulation.>

A general and efficient preprocessing algorithm which can increase circuit simulation efficiency is discussed. The algorithm identifies significant devices based upon circuit topology. Device model complexity and error tolerances are varied based upon device significance which results in a reduction in the required model evaluation time.>

This tutorial presents an overview of timing verification techniques which are used in the synthesis of IC layout.Issues which are covered include: delay estimation, transistor sizing, timing-driven placement and routing, circuit extraction, timing analysis and timing simulation.The role of each of these analysis techniques in the design flow is presented and numerous examples of associated CAD tools are described.

Article Utilizing logic information in multi-level timing simulation Share on Authors: Marko P. Chew Actel Corporation, 955 E. Arques Ave, Sunnyvale, CA and Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Actel Corporation, 955 E. Arques Ave, Sunnyvale, CA and Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Andrzej J. Strojwas Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 215–218https://doi.org/10.1145/127601.127667Online:01 June 1991Publication History 0citation48DownloadsMetricsTotal Citations0Total Downloads48Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

geometry and field Database (CDB), for representing the results of IC process and device simulation, and its use in the PREDITOR process editor and statistical simulator.Using fast analytical models, process simulation and device parameter extraction for a CMOS inverter takes 1.3sec on a DECstation 3100, with database access taking 14-34% of that time.

An efficient methodology for performing fault simulation experiments as part of an IC failure diagnosis system is described. The methodology uses regression models that relate IC performance directly to process disturbances inherent in all IC fabrication processes. An efficient algorithm for establishing the structure of such models based on data obtained from coupled process and circuit simulators is developed. It selects a minimum number of significant input parameters and automatically establishes an optimum order polynomial regression model. Moreover. the regression models obtained contain information about the structure of the dependence of IC performances on the process disturbances, which can be coded in a dependency tree for each IC performance and used directly for diagnostic purposes. The algorithm belongs to the class of artificial neural network approaches and has been implemented in a program called MULREG (multilayer regression). Two examples of analyzing MULREG are given.>

The authors present a numerically efficient mathematical approach, the numerical integral method, for diffusion modeling. This method extends the boundary integral methods to solve linear and nonlinear diffusion problems with physically based diffusivity models to account for concentration-dependent effects, oxidizing ambient effects, electric field effects, etc. The algorithm for solving nonlinear diffusion problems and its implementation in a computer program are described. Results from example problems are shown. This new numerical method provides the potential for achieving a diffusion simulation which is computationally efficient, numerically stable, and sufficiently accurate in an engineering environment. Such an efficient and yet accurate diffusion simulation is especially important in statistical simulation of VLSI processes.>

Random fluctuations in very large scale integrated circuit (VLSIC) fabrication processes cause the parametric production yield to fall below acceptable levels, resulting in a loss of competitive edge. To address this problem, a framework for an integrated computer-aided-design-computer-aided-manufacturing (CAD-CAM) system that will enable the design, fabrication, control, and diagnosis of present and future VLSICs to be carried out profitably is proposed. It is argued that the inefficiencies of present-day CAM systems are due to the lack of appropriate methodologies for process monitoring and statistical techniques to analyze the in-process and end-of-process data. Methodologies for monitoring lots in fabrication lines, using in situ measurements, and for controlling lots, using the multivariate distribution of observable in-process parameters, are discussed. These methodologies attempt to eliminate the pitfalls of the previous statistical process control algorithms. The software system that implements the algorithms has shown encouraging results when applied to industrial fabrication lines.

A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. The availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.

This tutorial focuses on the design strategies for VLSI circuits that are aimed at achieving manufacturable, high-yielding chips. We review the current status of statistical design methodologies based upon statistically-valid modeling and process characterization approaches. Both parametric and functional yield maximization strategies are covered. This tutorial argues that by providing a better starting point for manufacturing, the profitability and competitiveness can be significantly improved.

Using a formal modeling of the signal interactions, a statistical timing simulator capable of detecting delay faults and computing delay defect distributions has been built. This tool produces the delay fault statistics which must be used by delay fault ATPG (automatic test pattern generation) tools if they are to model process-induced delay failures realistically. The most obvious application for this tool is the computation of the probability of failure due to parametric delay faults. For this application, a Monte Carlo experiment was performed with a single nominal simulation followed by many timing reevaluations.>

This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A methodology based upon the utilization of the design hierarchy for circuit partitioning and building of the simulation hierarchy was developed. The logic and timing behaviors of the blocks resulting from the partitioning are dissociated and modeled separately. The logic model is represented by an equivalent finite state machine while an automated characterization process extracts the timing data from multiple circuit simulations in order to build a parametric timing model. These models provide the basis of an event-driven hierarchical timing simulator which can be used as a stand-alone tool but also as a front end for statistical timing analyses. Both the nominal and the statistical simulators have been implemented within STAT! (Statistical Timing Analysis Tool), and the results obtained for a few test cases are presented here.

This paper presents a general methodology for designing optimal test structures and their applications to characterize the process fluctuations inherent in IC manufacturing. A set of test structures, including a novel test structure, is presented in which each test structure parameter is sensitive to a minimal number of process parameters. The procedure for device parameter extraction is described. Optimal device dimensions, criteria for choosing the sample sizes of test structures, and test chips are also determined based upon statistical hypothesis testing techniques. This methodology is illustrated by an application for tuning of the statistical process/device simulator FABRICS II to a typical NMOS fabrication process.

This paper presents a methodology for determining the probability of structural failures for VLSI circuits. An analytically based approach is used to perform simulations accurately and efficiently. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometrical variations and local defects. A hierarchical model is proposed to describe the defect statistics including clustering. Strict analytical methods are used to find probabilities of failure for simple layout patterns. Then, the probability of failure for macrocells are calculated hierarchically. This methodology has been implemented in a CAD tool called RYE (Realistic Yield Evaluator). To demonstrate the effectiveness of this tool, the simulation results of several examples and the CPU time comparisons with Monte Carlo methods are also presented in this paper.

No abstract available.

In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both during the design process and during the manufacturing process. This framework is general enough to bridge the gap between the traditional concepts of parametric and catastrophic yield. We provide a classification of causes of yield loss which is essential for efficient yield estimation. Finally, we relate yield to manufacturing costs which provides a common denominator for the discussion of the manufacturing process efficiency.

Worst-case analysis is one of the most often used techniques for verifying that the sensitivity of integrated circuit (IC) performances to changes in manufacturing conditions is minimized. However, worst-case analysis is often carried out in terms of a correlated set of parameters, which results in a design that is unnecessarily pessimistic. This paper presents a new approach to the worst-case analysis of integrated circuits that results in more realistic estimates of variations in device and circuit performances. In particular, worst-case analysis is performed in terms of a set of statistically independent process disturbances. A software package for worst-case analysis is described and illustrated by a number of examples. The results of the proposed worst-case analysis method are compared to Monte Carlo simulations.

In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. The focus of the proposed approach is the concept of a statistical design rule, which is defined as a geometric design rule with an associated probability of failure. Global lateral variations obtained from FABRICS, and local spot defects obtained from measurements are taken into account when calculating the probability of failure. A failure model which accounts for catastrophic faults has been enhanced to include some parametric faults. STRUDEL can be used as a guide to generate layout design rules and may be extended to a wide range of applications including coarse yield estimation during design rules check.

This paper describes a software system for Computer Aided Manufacturing (CAM) of VLSI circuits being developed at Carnegie-Mellon University. In developing the system, a major effort was devoted towards the computational efficiency of the algorithms implemented. The results obtained with this system indicate that it can be used for a variety of real-life tasks, such as optimal process design, process diagnosis and control, in commercial fabrication lines. We believe that such a system provides an attractive extension for the CAM systems that are currently being introduced to VLSI fabrication processes.

Random fluctuations which are inherent in the IC manufacturing process cause production yields to be significantly less than 100 percent. Yield drop is caused by two types of faults, catastrophic and parametric. This paper deals with the diagnosis of parametric faults which occur during the manufacturing of IC's and cause the yield to drop below some acceptable level. A statistical pattern recognition approach to IC failure analysis is developed in this paper. Identification of faults is based on the analysis of the joint probability density function of circuit performances. A number of alternative approaches to IC failure analysis are developed and their efficiency is discussed. Also a complete statistical pattern recognition system with learning capability is proposed and all the stages of its development are discussed. An efficient method for fault simulation which is based upon statistical process simulation is proposed. The performance of the algorithms proposed in this paper has been successfully verified for data collected from commercial fabrication processes and from computer simulation.

This paper describes FABRICS II, an IC fabriction process simulator which takes into account the statistical fluctuations inherent in the manufacturing process. FABRICS II is composed of two parts, a fabrication process simulator FAB1, and a semiconductor device simulator FAB2. The simulator produces model parameters of typical semiconductor devices manufactured in various fabrication processes (NMOS, CMOS, or bipolar). Possible applications of FABRICS II include verification and optimization of process and circuit design, yield prediction and maximization prior to IC fabrication, and IC failure analysis. Two examples which illustrate the application of FABRICS II are presented.

Information about the random behavior of the IC manufacturing process can be applied for IC and process design tasks. In this paper a methodology for modeling random fluctuations of IC manufacturing process is proposed. A simulator of a complete bipolar manufacturing process called FABRICS, is described. A few applications illustrating advantages of the proposed statistical process modeling method are discussed.