In designing a mm-wave ultra-wideband pulse-Doppler radar IC, one of the main challenges encountered is to reduce the high power consumption of the circuitries in the IC. A direct-RF receiver can be used in the radar’s design to reduce the radar’s power consumption. However, a digitizer that can directly digitize mm-wave ultra-wideband radar pulses is needed to implement such a receiver. This work presents the design of such a digitizer, which comprises several multi-pass sub-ADCs that operate together. Each multi-pass sub-ADC works fundamentally like a flash ADC but comprises one comparator only. A test chip containing a 6-bit prototype of the digitizer is fabricated in a 40 nm CMOS technology. The prototype consumes 19.7 mW when operated at 4 GSa/s and can operate with input signal frequencies of up to 64 GHz while achieving a −1.7/−6 dBFSSNDRof 21.1/22.8 dB at 60 GHz (the correspondingFoMis 532/434 fJ/c-s). The digitizer has a relatively high effective parallel-equivalent input impedance at 60 GHz, which, in a radar IC implementation, allows it to be driven with a relatively low power-consuming 60 GHz RF buffer. These are achieved without the digitizer being fabricated in a much more advanced technology node.

Event camera is an emerging imaging sensor for capturing dynamics of moving objects as events, which motivates our work in estimating 3D human pose and shape from the event signals. Events, on the other hand, have their unique challenges: rather than capturing static body postures, the event signals are best at capturing local motions. This leads us to propose a two-stage deep learning approach, called EventHPE. The first-stage, FlowNet, is trained by unsupervised learning to infer optical flow from events. Both events and optical flow are closely related to human body dynamics, which are fed as input to the ShapeNet in the second stage, to estimate 3D human shapes. To mitigate the discrepancy between image-based flow (optical flow) and shape-based flow (vertices movement of human body shape), a novel flow coherence loss is introduced by exploiting the fact that both flows are originated from the identical human motion. An in-house event-based 3D human dataset is curated that comes with 3D pose and shape annotations, which is by far the largest one to our knowledge. Empirical evaluations on DHP19 dataset and our in-house dataset demonstrate the effectiveness of our approach.

This work introduces a pixel rendering module (PRM) into an asynchronous event-based dynamic vision sensor (DVS) targeting for optical flow extraction. Optical flow using event-based cameras draws more attention since DVSs directly provide motion related information related and greatly reduce the data redundancy compared to conventional frame-based cameras. Although event-based optical flow has a high potential on real-time performance, its accuracy is limited by event sparseness and lack of intensity, especially for fast motion and highly textured areas. This paper presents a motion sensor with PRM and asynchronous gray-level events to settle these issues. The PRM enables each pixel to communicate with its neighbor pixels such that a single active pixel can force activate its neighboring inactive pixels to provide sufficient data for optical flow calculation. Furthermore, the sensor outputs asynchronous event packages including pixel position, time-stamp and its corresponding illumination. A 64 × 64 prototype was fabricated in 0.35um 2P4M Opto process. Each pixel occupies a footprint of 40 × 40 μm2with 17 7% fill factor.

A star sensor has become one of the most widely used attitude sensors for the satellite missions in the past decade. When no prior attitude information is available, it operates in a Lost-in-space (LIS) mode. The star pattern recognition technique forms the most crucial part of star sensor in the LIS mode. In this paper, we propose a novel star pattern recognition technique for an LIS mode star sensor. Firstly, a discrete sample signal is formed from the features extracted from the star image. Later, a 1D FFT is applied on the discrete sample signal. Finally, a binary pattern is formed from the relative magnitude of consecutive FFT coefficients for finding a match between the image and the database. Experiments are performed on simulated star images with missing and false stars. The proposed approach robustly maintains the identification accuracy to 97% on the swayed and biased simulated images.

In this paper, we propose an event-guided support vector machine (ESVM) for tracking high-speed moving objects. Tracking fast-moving objects with low frame rate cameras is always difficult due to motion blur and large displacements. The accuracy problem can be solved by using high frame rate cameras at the expense of tremendous computational cost. For this issue, our ESVM incorporates event-based guiding methods into the traditional structured support vector machine to improve the tracking accuracy at a relatively low-complexity level. The event-based guiding methods include two models, event position guided search localization and event intensity guided sample supplement, which are based on the event features of the CeleX motion sensor. The motion sensor continuously responds to intensity change, which is generally related to object motion. Once it has detected intensity change, the motion sensor outputs event packages, and each of them contains the pixel location, time stamp, and pixel illumination. The generated events are continuous in the temporal domain and thus record the motion trajectory of fast-moving objects, which cannot be fully captured by frame-based cameras. In this paper, we convert high-speed test sequences into sequences of spiking events recorded by the CeleX motion sensor. Our approach presents fairly high computational efficiency, and experiments over sequences from multiple tracking benchmarks demonstrate the superior accuracy and real-time performance of our method, compared to the state-of-the-art trackers.

High accuracy is required for determining the orientation of a satellite in space. Amongst the existing sensors, a star tracker provides a very high accuracy of attitude determination. When no prior attitude is available, it operates in the “Lost-In-Space (LIS)” mode. Star pattern recognition is the most crucial part of a star tracker in the LIS mode. In this paper, a novel star pattern recognition approach is proposed, which constructs a signal from the features extracted in the star image and utilizes spearman correlation for identifying the correct stars. The proposed technique achieves a high identification accuracy of 99.67%. The results from the simulations show that this technique is also highly recognition reliable to the cases of missing stars, deviation in star positions, magnitude uncertainty, and false stars compared to the existing star identification algorithms.

We demonstrate a high resolution Dynamic Vision Sensor (DVS) with 768 × 640 pixels, and 200Meps (event per second) high speed readout. The sensor has a dual-channel synchronous interface and can operate at 100 MHz. It has a few unique features, namely three-in-one (coordinate, brightness and time stamp) event packet, capability of producing full-array picture-on-demand [1] and on-chip optical flow computation. The sensor will find broad applications in real-time machine vision.

This paper presents a Dynamic Vision Sensor with a few interesting features. We directly readout the voltage on the logarithmic photo detector as the intensity information of the fired pixel. The computer is able to command the sensor to produce a full-frame picture at whatever time it needs. The sensor was implemented using AMS 0.35 μm 2P4M Opto process with an array of 384 × 320 pixels. Each pixel occupies a footprint of 30 × 30 μm2, with 12% fill factor.

We propose a track-and-hold-less flash-like stroboscopic ADC for use in the implementation of an undersampling ultra-wide-band radar receiver. The ADC is comprised of a number of sub-ADCs in which each sub-ADC is a multi-pass ADC. Strong-Arm latch with tens of GHz of sampling bandwidth is utilized as the core of each multi-pass ADC. The prototype of the ADC achieves a THD of ~23dB with a THD ERBW of > 50 GHz when the input signal swing is ~135 mVpp. The total power consumption of the prototype is ~10 mW when it is operated under a 1 GHz clock giving it an FOM of ~0.87 pJ/cs.

We demonstrate a new Dynamic Vision Sensor (DVS) with 192 × 160 pixels. The sensor has a synchronous interface and can operate at 40 MHz. The pixel event packet consists of three elements: pixel address, time stamp and its intensity. The sensor is able to produce full-array picture-on-demand. These two unique features will favor subsequent signal processing algorithms such as object tracking and optical flow.

This paper presents a dynamic resolution asynchronous event-based dynamic vision sensor(DVS) that benifits from low power consumption. Pixel core in this kind of sensor can be divided into two parts: photoreceptor and motion detection circuit. In this design, power is kept low by turning off some pixels' motion detection circuits when there is no event nearby. The full resolution of this sensor is 64 × 64. There are two working states of the sensor: 1.coarse motion detection and 2.fine detection in the region of interest (ROI). In the first state, each 4×4 pixels are grouped into a pixel block. Their photoreceptors are connect together, sharing only one motion detection circuit to monitor motion in the block region. When a block detects event, the other fifteen pixels in the block are powered up and work individually. Higher resolution image of the ROI is sent out via address event representation (AER) protocol. When no more event is detected in this region, the block goes back to state 1. Simulation result shows that the average power can be reduced to 1/9 of the conventional fixed-resolution DVS. This sensor is fabricated using AMS 0.35μm 4M2P CMOS process. Each pixel contains 3 capacitors and 60 transistors, occupying a silicon area of 34×34μm2, with a fill factor of 15.6%.

A star tracker is a critical sensor for determining and controlling the attitude of a satellite. It utilizes a complementary metal–oxide–semiconductor (CMOS)-active pixel sensor to map the star field onto the focal plane. Starlight is measured and star centroids are calculated to estimate attitude knowledge. In this paper, we present a CMOS image sensor for star centroid measurement in star trackers. To improve sensitivity to low-level starlight, the capacitive transimpedance amplifier pixel is used as the detector. To improve centroiding accuracy, the proposed sensor architecture allows star pixels, pixels that are above a star threshold, to cluster together. The mean value of all the pixels in this cluster is calculated. The star signals are then amplified in relation to this mean value. This increases the signal-to-noise ratio in star regions in line with their starlight intensity. An adaptive region-of-interest readout architecture is also proposed, which reports only star regions instead of the entire frame. The proof-of-concept chip, containing a$128 \times 128$pixel array, was fabricated using AMS 0.35-$\mu \text{m}$CMOS Opto process. Each pixel has a size of$31.2 \times 31.2~\mu \text{m}^{2}$. The measurement results show that centroiding accuracy increases with higher centroiding gain. Within a limited exposure time, the relative centroiding accuracy can surpass that of a commercial image sensor by more than 1%.

This paper presents an antivibration time-delay integration (TDI) CMOS image sensor (CIS) for small remote imaging systems, introducing a hardware-implemented online deblurring (ODB) algorithm to address the image blur problems caused by vibrations. The proposed sensor has eight TDI stages, column-parallel TDI accumulating and ODB circuits. A$256\times 8$-pixel prototype chip was fabricated using a 0.18-$\mu \text{m}$CIS technology with a pixel footprint of$6.5~\mu {\mathrm{ m}}\times 6.5~\mu \text{m}$and a fill factor of 28%. Measurement results show that the sensor can achieve dynamic ranges of 45.1 and 51.8 dB, respectively, with and without enabling the ODB algorithm. Compared with a single-stage line scanner imager, it offers an improvement in signal-to-noise ratios of 1.9 and 8.6 dB, respectively, with and without the ODB algorithm.

Machine vision applications involving the assistance of robots for scene mapping or object classification encounter issues when faced with smooth transparent surfaces, such as glass. Specular reflection from such surfaces saturate the image sensor pixels, restricting their vision of objects beyond the surface. The problem is aggravated by the movement of the robot, making traditional approaches unfeasible. We propose a solution that uses on-chip polarizers to limit the specular reflection and improve scene visibility while overcoming the limited SNR and motion artifacts by using a time delay integration image sensor. We have fabricated a 256×8×5 prototype sensor using a 0.18μm CIS process which achieves a DR of 52.3dB while providing an SNR improvement of 8.8dB over a single-stage linear scanner.

Ring oscillator (RO)-based physical unclonable function (PUF) is resilient against noise impacts, but its response is susceptible to temperature variations. This paper presents a low-power and small footprint hybrid RO PUF with a very high temperature stability, which makes it an ideal candidate for lightweight applications. The negative temperature coefficient of the low-power subthreshold operation of current starved inverters is exploited to mitigate the variations of differential RO frequencies with temperature. The new architecture uses conspicuously simplified circuitries to generate and compare a large number of pairs of RO frequencies. The proposed nine-stage hybrid RO PUF was fabricated using global foundry 65-nm CMOS technology. The PUF occupies only 250 μm2of chip area and consumes only 32.3 μW per challenge response pair at 1.2 V and 230 MHz. The measured average and worst-case reliability of its responses are 99.84% and 97.28%, respectively, over a wide range of temperature from -40 to 120 °C.

This paper introduces an event-driven feedforward categorization system, which takes data from a temporal contrast address event representation (AER) sensor. The proposed system extracts bio-inspired cortex-like features and discriminates different patterns using an AER based tempotron classifier (a network of leaky integrate-and-fire spiking neurons). One of the system's most appealing characteristics is its event-driven processing, with both input and features taking the form of address events (spikes). The system was evaluated on an AER posture dataset and compared with two recently developed bio-inspired models. Experimental results have shown that it consumes much less simulation time while still maintaining comparable performance. In addition, experiments on the Mixed National Institute of Standards and Technology (MNIST) image dataset have demonstrated that the proposed system can work not only on raw AER data but also on images (with a preprocessing step to convert images into AER events) and that it can maintain competitive accuracy even when noise is added. The system was further evaluated on the MNIST dynamic vision sensor dataset (in which data is recorded using an AER dynamic vision sensor), with testing accuracy of 88.14%.

This paper presents a fully event-driven feedforward architecture that accounts for rapid categorization. The proposed algorithm processes the address event data generated either from an image or from Address-Event-Representation (AER) temporal contrast vision sensor. Bio-inspired, cortex-like, spike-based features are obtained through event-driven convolution and neural competition. The extracted spike feature patterns are then classified by a network of leaky integrate-and-fire (LIE) spiking neurons, in which the weights are trained using tempotron learning rule. One appealing characteristic of our system is the fully event-driven processing. The input, the features, and the classification are all based on address events (spikes). Experimental results on three datasets have proved the efficacy of the proposed algorithm.

The globalization of integrated circuits (ICs) design and fabrication has given rise to severe concerns on the devastating impact of subverted chip supply. Hardware Trojan (HT) is among the most dangerous threats to defend. The dormant circuit inserted stealthily into the chip by the advisory could steal the confidential information or paralyze the system connected to the subverted chip upon the HT activation. This paper presents a transient power supply current sensor to facilitate the screening of an IC for HT infection. Based on the power gating scheme, it converts the current activity on local power grid into a timing pulse from which the timing and power-related side channel signals can be externally monitored by the existing scan test architecture. Its current comparator threshold can be calibrated against the quiescent current noise floor to reduce the impacts of process variations. Postlayout statistical simulations of process variations are performed on the ISCAS'85 benchmark circuits to demonstrate the effectiveness of the proposed technique for the detection of delay-invariant and rarely switched HTs. Compared with the detection error rate of a 4-bit counter-based HT reported by an existing HT detection method using the path delay fingerprint, our method shows an order of magnitude improvement in the detection accuracy.

With the globalization of integrated circuit (IC) design and fabrication, there is a growing concern on the devastating impact of subverted chip supply. This paper presents a current sensing circuit that converts the current activity on local power grid to a timing pulse to detect if an IC is Trojan-infected. This new approach increases the Trojan detection sensitivity by combining the switching activity and path sensitization abnormalities into a single side-channel signal that can be easily monitored by existing scan test structure. One main advantage of the proposed regional Trojan detector is that the current comparator threshold can be calibrated against the quiescent current noise floor to reduce the impacts of process variations. Experiments are performed on a Trojan-infected benchmark circuit to demonstrate the feasibility of the proposed technique.

We demonstrate an asynchronous address event representation (AER) motion detection sensor [1][2], that only responds to motions with speed higher than a tunable threshold. Each pixel in the sensor can individually monitor the relative change in light intensity and report a digital event if a threshold is reached. The output of the sensor is not a frame, but a stream of asynchronous digital events. By adjusting a variable slow-motion filter, low speed motion can be filtered.

Event-driven visual sensors have attracted interest from a number of different research communities. They provide visual information in quite a different way from conventional video systems consisting of sequences of still images rendered at a given "frame rate." Event-driven vision sensors take inspiration from biology. Each pixel sends out an event (spike) when it senses something meaningful is happening, without any notion of a frame. A special type of event-driven sensor is the so-called dynamic vision sensor (DVS) where each pixel computes relative changes of light or "temporal contrast." The sensor output consists of a continuous flow of pixel events that represent the moving objects in the scene. Pixel events become available with microsecond delays with respect to "reality." These events can be processed "as they flow" by a cascade of event (convolution) processors. As a result, input and output event flows are practically coincident in time, and objects can be recognized as soon as the sensor provides enough meaningful events. In this paper, we present a methodology for mapping from a properly trained neural network in a conventional frame-driven representation to an event-driven representation. The method is illustrated by studying event-driven convolutional neural networks (ConvNet) trained to recognize rotating human silhouettes or high speed poker card symbols. The event-driven ConvNet is fed with recordings obtained from a real DVS camera. The event-driven ConvNet is simulated with a dedicated event-driven simulator and consists of a number of event-driven processing modules, the characteristics of which are obtained from individually manufactured hardware modules.

Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-powerMLsense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore, we propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.

A new scheme for human posture recognition is proposed based on analysis of key body parts. Utilizing a time-of-flight depth camera, a pulse coupled neural network (PCNN) is employed to detect a moving human in cluttered background. In the posture recognition phase, a hierarchical decision tree is designed for classification of body parts so that the 3D coordinate of the key points of the detected human body can be determined. The features described in each individual layer of the tree can be chained as hierarchical searching indices for retrieval procedure to drastically improve the efficiency of template matching in contrast to conventional shape-context method. Experimental results show that the proposed scheme gives competitive performance as compared with the state-of-the-art counterparts.

We present a non-coherent wireless communication testing platform for ultra wide-band impulse radio (UWB-IR) with frequency-shift-keying (FSK) on-off-keying (OOK). Both transmitter and receiver platform will be present with a control graphic user interface (GUI) supported by Spartan-3 FPGAs. The transmitter chip is integrated while the receiver is build from off-the-shelf components. Monopole antennas are used in the system. The demonstration shows a transformative wireless communication technology for low power low cost short range applications.

In this paper, we report a novel Time-Delay-Integration (TDI) CMOS image sensor for low-earth orbit (LEO) nano-satellite imaging application, where limited exposure time and unexpected flight fluctuations are major design challenges. The sensor features programmable integration time per stage, dynamic charge transfer path and tunable well capacity. A prototype chip of 1536×8 pixels was implemented using TSMC 0.18µm CMOS image sensor process. Photodiode and other transistors are floor-planned in different arrays, providing small pixel pitch of 3.25µm and high fill factor of 57%.

This paper presents a hybrid-readout and dynamic-resolution CMOS image sensor targeted for object tracking applications. The proposed vision sensor can either work in an asynchronous motion detection mode or synchronous region of interest (ROI) readout mode, with different resolutions. In the first mode, relative intensity changes are monitored by a motion detection unit formed of 2×2 pixels and further diffused by a capacitance coupling network to reduce spatial noise. After tunable thresholding, active motions are converted into binary events and asynchronously delivered to the outside using an address-event-representation (AER) protocol. In the ROI extraction mode, this image sensor sequentially accesses each pixel in the interested region to report an analog intensity image with a higher resolution. This sensor has been implemented using a standard 0.18 µm CMOS process. Each pixel contains three capacitors and around 10 transistors, occupying a silicon area of 25×25 µm2, with a fill factor of ∼42%.

We demonstrate a real-time moving object localization and extraction system. The system consists of a 256 × 256 CMOS image sensor and an Opal-Kelly FPGA board. Frame differencing is utilized for motion detection; a stream of binary motion events are generated and further fed to a clustering-based object localization unit, where each event is processed on the fly. At the end of one frame, the moving object region is immediately localized and an image of that region is extracted.

This paper proposes an algorithm for feedforward categorization of objects and, in particular, human postures in real-time video sequences from address-event temporal-difference image sensors. The system employs an innovative combination of event based hardware and bio-inspired software architecture. An event-based temporal difference image sensor is used to provide input video sequences, while a software module extracts size and position invariant line features inspired by models of the primate visual cortex. The detected line features are organized into vectorial segments. After feature extraction, a modified line segment Hausdorff distance classifier combined with on-the-fly cluster-based size and position invariant categorization. The system can achieve about 90 percent average success rate in the categorization of human postures, while using only a small number of training samples. Compared to state-of-the-art bio-inspired categorization methods, the proposed algorithm requires less hardware resource, reduces the computation complexity by at least five times, and is an ideal candidate for hardware implementation with event-based circuits.

This paper presents a 64×64 CMOS image sensor with on-chip moving object detection and localization capability. Pixel-level storage elements (capacitors) enable the sensor to simultaneously output two consecutive frames, with temporal differences digitalized into binary events by a global differentiator. An on-chip, hardware-implemented, clustering-based algorithm processes events on the fly and localizes up to three moving objects in the scene. The sensor can automatically switch to region of interest mode and capture a picture of the object. The proposed image sensor was implemented using UMC 0.18 μm CMOS technology with a die area of 1.5 mm × 1.5 mm, and power consumption was only 0.4 mW at 100 FPS.

In this paper we present a low power temporal-difference image sensor with wireless communication capability designed specifically for imaging sensor networks. The event-based image sensor features a 64 × 64 pixel array and can also report standard analog intensity images. An ultra-wide-band radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rates and reduced power consumption. The sensor can wake up the radio when it detects a specific number of pixels intensity modulation, so that only significant frames are communicated. The prototype chip was implemented using a 2-poly 3-metal AMIS 0.5 μ m CMOS process. Power consumption is 0.9 mW for the sensor and 15 mW for radio transmission to distance of 4 m with rates of 1.3 Mbps and 160 fps.

Robust, high-performance and low-power match-line sense amplifier designs are urgently required to catch up with the new requirements of large-scale CAMs in nano-scale CMOS technologies. In this paper we evaluate the performance of four state-of-the-art match-line sense amplifier designs in terms of power, delay and robustness against temperature, supply voltage and process variations. Our results show that the pre-charge low match-line sensing schemes suffers from process variations. Despite featuring low power consumption, these designs can hardly be scaled down to operate in low-voltage sub-65 nm CMOS process. On the other hand, the conventional and the charge-injection designs are much more robust and hence more suitable for low-voltage sub-65 nm CMOS implementations.

People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects that are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application.

In a Content Addressable Memory (CAM) architecture, both the match-line (ML) sensing circuit and the priority encoder (PE) contribute significantly large delays during a compare cycle. Meanwhile the priority encoder consumes significantly less energy when compared to the sensing circuits, i.e. ~1% of the overall energy consumption. Based on this observation, we propose the use of dual-supply voltages to trade-off the power and delay budget between the comparison and priority encoding circuits. In this work, the memory array and priority encoder is powered by a low and a high supply voltage, respectively. On top of this, a self-power-off ML sense amplifier is employed to reduce the voltage swing on the ML buses. Simulation results show a 76% dynamic power reduction as compared to the conventional design without sacrificing the overall speed.

This paper presents a realtime feature extraction processor based on MAX-like convolutional network. Due to the massive parallel MAX operations across multiple layers of feature maps, conventional implementation requires a vast amount of memory access as well as computation circuits. By exploring the overlapped data and reusing the intermediate computation results between consecutive "neurons", tremendous saving in both memory bandwidth and hardware resource has been achieved. Experimental results show that the number of logic gates drops from 402k to 170k, compared to conventional approach. The proposed feature extraction processor can be integrated with a custom-designed motion detection image sensor and a hardware-accelerated classifier to perform realtime human posture recognition.

In this paper, we reported an adaptive priority toggle asynchronous tree arbiter for Address Event Representation (AER)-based image sensors. Simultaneous requests from event-triggered pixels, event latency, timing error and jitter are the inherent issues in AER-based read-out circuits. Fixed priority arbiter often results in unfair allocation of bus resource to only “privileged” pixels thus resulting in timing error. The proposed arbiter is able to reduce the timing error by toggling the requests priority during simultaneous requests. This also achieves the fair allocation of bus resource to all pixels. The featured eager propagation scheme allows the requests to propagate towards higher hierarchy in the tree during the arbitration process. As a result, latency and jitter problems can be reduced. Simulation result reveals that single event delay for 128-way tree arbiter is 4.2 ns and therefore, for 128 × 128 array, such arbiter can process up to 238.09M event/s which is more than 15 times faster than the speed of the reported AER sensor. The arbiter layout was realized with 2P4M 0.35µm CMOS process with a silicon area of 78 × 18µm2and had been implemented in 80 × 80 array AER temporal contrast sensor.

This paper presents the architecture, algorithm, and VLSI hardware of image acquisition, storage, and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. The pixel-level memory is used to store the uncompressed illumination data during the integration mode as well as the compressed illumination data obtained after the compression stage. An adaptive quantization scheme based on fast boundary adaptation rule (FBAR) and differential pulse code modulation (DPCM) procedure followed by an online, least storage quadrant tree decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64×64 pixels, read-out and control circuitry as well as an on-chip compression processor was implemented in 0.35 μm CMOS technology with a silicon area of 3.2×3.0 mm2and an overall power of 17 mW. Simulation and measurements results show compression figures corresponding to 0.6-1 bit-per-pixel (BPP), while maintaining reasonable peak signal-to-noise ratio levels.

We demonstrate a low power temporal-difference image sensor with wireless communication capability designed specifically for imaging sensor networks. The event-based image sensor features a 64×64 pixel array and can also report standard analog intensity images. An ultra-wide-band (UWB) radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rates and reduced power consumption. The sensor wakes up when it detects enough scene changes and only communicates meaningful frames. A complete demo platform, for both the wireless sensor (transmitter) and a receiver was developed. Power consumption is 0.9 mW for the sensor and 15 mW for radio transmission to 4 m with rates of 1.3 Mbps and 160 fps.

In this paper we present a low power temporal-difference image sensor with wireless communication capability designed specifically for imaging sensor networks. The event-based image sensor features a 64 × 64 pixel array and can also report standard analog intensity images. An ultra-wideband (UWB) radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rates and reduced power consumption. The sensor wakes up when it detects enough scene changes and only communicates meaningful frames. Power consumption is 0.9 mW for the sensor and 15 mW for radio transmission to 4 m with rates of 1.3 Mbps and 160 fps.

This paper proposes a new approach to recognize human postures in realtime video sequences. The algorithm employs temporal difference imaging between video sequences as input and then decompose the contour of the active object into vectorial line segments. A scheme based on simplified line segment Hausdorff distance combined with projection histograms is proposed to achieve size and position invariance recognition. Consistent with the hierarchical model of the human visual system, sub-sampling techniques are used to represent the object by line segments at multiple resolution levels. The whole classification is described as a coarse to fine procedure. An average realtime recognition rate of 88% is achieved in the experiment. Compared to conventional convolution method, the proposed algorithm reduces the computation cycles by 10 - 100 times. This work sets the foundation for size and position invariant object recognition for the implementation of event-based vision systems.

We demonstrate a realtime human postures recognition platform. The algorithm employs temporal difference imaging between video sequences as input and then decompose the contour of the active object into vectorial line segments. A scheme based on simplified line segment Hausdorff distance combined with projection histograms is proposed to achieve size and position invariance recognition. Inspired by the hierarchical model of human visual system, the whole classification is described as a coarse to fine procedure. 88% average realtime recognition rate is achieved in the experiment.

This paper presents a fast algorithm for generating Hilbert address for hardware implementation with low storage requirement. This work avoids the use of recursive functions as compared with Quinqueton's work, and eliminates complicated bit manipulations as proposed by Butz, and does not use any look-up-tables as implemented by Kamata. Each address can be obtained in one clock cycle by one-to-one mapping using a simple incremental counter and cascading of multiplexers. The merit of our method is that it achieves very high speed when computing the Hilbert address which requires little memory storage.

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1times0.6 mm2). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35 mum process with a silicon area of 3.1times3.2 mm2. Successful operation of the prototype is illustrated through experimental measurements

In this paper we propose a second generation time-to-first-spike (TFS) pixel based on an asynchronous self power-off architecture. In this architecture time-to-first spike is used to encode the photocurrent information. Once the first spike is received and read-out using an address event representation (AER), the pixel is forced into standby mode by cutting off the power supply of itself. Simulation results shows that significant reduction in leakage power is achieved which is a major concern when implementing high resolution image sensor in deep-submicron technology. Based on this proposed architecture a prototype was designed in UMC 0.18 /spl mu/m technology. Each pixel includes a photodiode, an event generator and hand-shaking communication protocol using 15 transistors. Each pixel occupies an area of 8.3 /spl times/ 8.3/spl mu/m/sup 2/ with a fill factor of 15%. In addition, the new generation TFS sensor features reduced depth of the arbitration tree using high-radix AER building block resulting in reduced overall delay.