The increasing complexity of CMOS technology and circuit designs has intensified the need for robust analog design automation tools that can handle process variations effectively. This paper presents RSizing, a novel approach for analog circuit sizing that optimizes performance while ensuring robustness against process variations. Our method employs a three-phase strategy: First, it identifies promising design regions through nominal condition optimization to prune the design space efficiently. Second, it performs variation-aware optimization using heteroscedastic Gaussian processes (HGP) to model circuit performance under process variations, capturing the non-uniform nature of process-induced fluctuations across the design space. The HGP models are combined with an efficient acquisition function based on Thompson sampling to guide the exploration of robust designs using limited Monte Carlo simulations. Finally, it refines the solutions through additional targeted Monte Carlo simulations and model calibration. Experimental results on three benchmark circuits demonstrate that RSizing achieves superior performance compared to existing methods, consistently meeting yield requirements while optimizing multiple performance metrics with significantly reduced computational cost.

This paper presents an analysis of differential-drive cross-coupled (DDCC) rectifier in high-sensitive RF energy harvesting system. The relationship between input RF voltage and output DC voltage with gate compensation voltage is built. Meanwhile, effects of mismatches on differential input branches are discussed. To verify the mismatch analysis, simulations on both the amplitude mismatch and the phase mismatch are conducted under standard CMOS 180nm process. Both theorical analysis and simulations indicate that the amplitude mismatch features little effect on the output DC voltage but the phase mismatch plays a much more important role to decrease the output voltage of DDCC rectifiers.

A current-reuse Gm-C complex filter is proposed in this paper. The bias current of input transconductor is reused to achieve both the load resistor and the transfer function's imaginary part. Meanwhile, in order to recalibrate the frequency response caused by the PVT effect, source degeneration technique is employed to realize robust effective gm which is proportional to 1/R. To demonstrate the proposed technique featuring good tuning capability and robustness to the process mismatch and variation, a first-order Gm-C complex filter was designed under the standard TSMC65nm CMOS, realizing a center frequency and a -3dB pass-band of 2MHz and 1.2MHz, respectively. The simulated results provide a mean image rejection ratio(IRR) of 16dB and a spurious-free dynamic range(SFDR) of 56.27dB. The Monte Carlo simulation indicates IRR features a minimum standard deviation of 0.426dB compared with the reported works. It has a power dissipation of 28.8μW from 1.2-V supply voltage.