Mayukh Nath

dblp:220/4318 · DBLP profile ↗
← Back
5ranked-venue papers
0as first author
4since 2021 · last 2023
0000-0002-0305-6048ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 since 2021Software engineering, systems software and programming languages · 2 · 1 since 2021
YearPublicationVenuePosition
2023 Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing
abstract
While cryptographic implementations provide computational security in circuits and systems, hardware attack techniques, e.g., electromagnetic (EM) side-channel analysis (SCA) attack can still break through. The commonplace countermeasures for EM SCA attack require significant overheads in terms of power consumption. This article explores an on-chip capacitive sensing technique for the purpose of detection of an approaching EM probe even before an attack is performed, thereby alleviating the overheads incurred by any countermeasure against such attacks. Different type of capacitive structures are considered in regards to sensitivity and area. The proposed method of coplanar capacitive asymmetry sensing (CEASE) consists of a grid of four metal plates of the same size and dimensions determined through design space exploration. A comparison between the capacitive and inductive sensing technique is also performed in terms of detection range through theoretical arguments and EM simulation. A$>$17% change in capacitance is shown at a distance of 1 mm, implying a$>10\times $improvement in the detection range over inductive sensing methods. Furthermore, at 0.1-mm distance, a$>$45% change in capacitance is observed, leading to a$>3\times $and$>11\times $sensitivity improvement over capacitive parallel plate sensing and inductive sensing, respectively.
Dong-Hyun Seo, Mayukh Nath, Debayan Das, Santosh Ghosh, Shreyas Sen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2022 EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation
abstract
This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows$>5\times $reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.
Debayan Das, Mayukh Nath, Baibhab Chatterjee, Raghavan Kumar, Xiaosen Liu, Harish Krishnamurthy, Manoj R. Sastry, Sanu Mathew, Santosh Ghosh, Shreyas Sen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2021 Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing
abstract
Electromagnetic (EM) side-channel analysis (SCA) attack, which breaks cryptographic implementations, has become a major concern in the design of circuits and systems. This paper focuses on EM SCA and proposes the detection of an approaching EM probe even before an attack is performed. The proposed method of co-planar capacitive asymmetry sensing consists of a grid of four metal plates of the same size and dimension. As an EM probe approaches the sensing metal plates, the symmetry of the sensing metal plate system breaks, and the capacitance between each pair diverge from their baseline capacitances. Using Ansys Maxwell Finite Element Method (FEM) simulations, we demonstrate that the co-planar capacitive asymmetry sensing has an enhanced detection range compared to other sensing methods. At a distance of 1 mm between the sensing metal plates and the approaching EM probe, it shows >17 % change in capacitance, leading to a > 10 × improvement in detection range over the existing inductive sensing methods. At a distance of 0.1 mm, a > 45% change in capacitance is observed, leading to a > 3 × and > 11 × sensitivity improvement over capacitive parallel sensing and inductive sensing respectively. Finally, we show that the co-planar capacitive asymmetry sensing is sensitive to both E-field and H-field probes, unlike inductive sensing which cannot detect an E-field probe.
Dong-Hyun Seo, Mayukh Nath, Debayan Das, Santosh Ghosh, Shreyas Sen
DATE2
2021 PG-CAS: Patterned-Ground Co-Planar Capacitive Asymmetry Sensing for mm-Range EM Side-Channel Attack Probe Detection
abstract
Electromagnetic (EM) side-channel analysis (SCA) attack, which breaks cryptographic implementations, has become a major concern in the design of circuits and systems. This paper presents the design and analysis of the EM side-channel attack detection system utilizing patterned-ground co-planar capacitive asymmetry sensing (PG-CAS) for approaching probe, targeting to improve sensitivity, detection range, and power consumption compared to LC oscillator utilizing inductive sensing. The PG-CAS consists of a grid of four metal plates of the same size at the top metal layer and a patterned ground plane at a lower metal. As an EM probe approaches, electric field lines between the plates and plate-ground get distorted, thereby breaking the symmetry of the inter-plate and the plate-ground capacitance system and this change in capacitance is sensed. The PG-CAS circuit consists of two LC oscillators, mixer, low pass filter (LPF), resistive feedback amplifier (RFA) and a digital logic. By down-converting sensing signal to low-frequency using mixer, LPF, RFA and digital logic, the detection range is significantly improved. At a distance of 1 mm between the sensing metal plates and the approaching EM probe, system-level simulation results using TSMC 65nm technology and Ansys Maxwell show a > 10% change in the output frequency from the baseline frequency, leading to a > 10× improvement in the detection range and a ~ 3× improvement in power consumption over existing inductive sensing methods.
Dong-Hyun Seo, Mayukh Nath, Debayan Das, Baibhab Chatterjee, Santosh Ghosh, Shreyas Sen
ISCAS2
2020 A 100KHz-1GHz Termination-dependent Human Body Communication Channel Measurement using Miniaturized Wearable Devices
abstract
Human Body Communication has shown great promise to replace wireless communication for information exchange between wearable devices of a body area network. However, there are very few studies in literature, that systematically study the channel loss of capacitive HBC for wearable devices over a wide frequency range with different terminations at the receiver, partly due to the need for miniaturized wearable devices for an accurate study. This paper, for the first time, measures the channel loss of capacitive HBC from 100KHz to 1GHz for both high-impedance and 50Ω terminations using wearable, battery powered devices; which is mandatory for accurate measurement of the HBC channel-loss, due to ground coupling effects. Results show that high impedance termination leads to a significantly lower channel loss (40 dB improvement at 1MHz), as compared to 50Ω termination at low frequencies. This difference steadily decreases with increasing frequency, until they become similar near 80MHz. Beyond 100MHz inter-device coupling dominates, thereby preventing accurate measurements of channel loss of the human body. The measured results provide a consistent wearable, wide-frequency HBC channel loss data and could serve as a backbone for the emerging field of HBC by aiding in the selection of an appropriate operation frequency and termination.
Shitij Avlani, Mayukh Nath, Shovan Maity, Shreyas Sen
DATE2