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Chihyun Song

dblp:220/5477 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0002-0414-9262ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 2 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Systems and software security · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security › operating system security
privilege separation
1.022023
Harnessing the x86 Intermediate Rings for Intra-Process Isolation · IEEE Trans. Dependable Secur. Comput. 2023
Lord of the x86 Rings: A Portable User Mode Privilege Separation Architecture on x86 · CCS 2018
Systems and software security › memory safety › memory isolation
in-process isolation
0.712023
Harnessing the x86 Intermediate Rings for Intra-Process Isolation · IEEE Trans. Dependable Secur. Comput. 2023
Systems and software security
memory safety
0.712023
Harnessing the x86 Intermediate Rings for Intra-Process Isolation · IEEE Trans. Dependable Secur. Comput. 2023
Processor architecture and microarchitecture
instruction set architecture
0.712023
Harnessing the x86 Intermediate Rings for Intra-Process Isolation · IEEE Trans. Dependable Secur. Comput. 2023
Systems and software security › trusted computing
trusted execution
0.112018
Lord of the x86 Rings: A Portable User Mode Privilege Separation Architecture on x86 · CCS 2018

Methods — techniques the papers use, named apart from their topics

x86 intermediate privilege rings · 2.0memory access control · 2.0x86 privilege rings · 0.3
YearPublicationVenuePosition
2023 Harnessing the x86 Intermediate Rings for Intra-Process Isolation
abstract
Modern applications often involve the processing of sensitive information. However, the lack of privilege separation within the user space leaves sensitive application secrets such as cryptographic keys just as unprotected as a ”hello world” string. Cutting-edge hardware-supported security features are being introduced. However, the features are often vendor-specific or lack compatibility with older generations of the processors. The situation leaves developers with no portable solution to incorporate protection for the sensitive application component. We propose LOTRx86, a fundamental and portable approach for user-space privilege separation. Our approach creates a more privileged user execution layer calledPrivUserby harnessing the underused intermediate privilege levels on the x86 architecture. The PrivUser memory space, a set of pages within process address space that are inaccessible to user mode, is a safe place for application secrets and routines that access them. We implement the LOTRx86 ABI that exports theprivcallinterface to users to invoke secret handling routines in PrivUser. This way, sensitive application operations that involve the secrets are performed in a strictly controlled manner. The memory access control in our architecture isprivilege-based, accessing the protected application secret only requires a change in the privilege, eliminating the need for costly remote procedure calls or change in address space. We evaluated our platform by developing a proof-of-concept LOTRx86-enabled web server that employs our architecture to securely access its private key during an SSL connection. We conducted a set of experiments, including a performance measurement on the PoC onbothIntel and AMD PCs, and confirmed that LOTRx86 incurs only a limited performance overhead.
Hojoon Lee 0001, Chihyun Song, Brent ByungHoon Kang
IEEE Trans. Dependable Secur. Comput.2
2021 hSDB-instrument: Instrument Localization Database for Laparoscopic and Robotic Surgeries
Jihun Yoon, Sunghwan Heo, Hayeong Yu, Jayeon Lim, Chihyun Song, SeulGi Hong, Seungbum Hong, Bokyung Park, Woo Jin Hyung, Min-Kook Choi
MICCAI (4)6
2018 Lord of the x86 Rings: A Portable User Mode Privilege Separation Architecture on x86
abstract
Modern applications often involve processing of sensitive information. However, the lack of privilege separation within the user space leaves sensitive application secret such as cryptographic keys just as unprotected as a "hello world" string. Cutting-edge hardware-supported security features are being introduced. However, the features are often vendor-specific or lack compatibility with older generations of the processors. The situation leaves developers with no portable solution to incorporate protection for the sensitive application component. We propose LOTRx86, a fundamental and portable approach for user-space privilege separation. Our approach creates a more privileged user execution layer called PrivUser by harnessing the underused intermediate privilege levels on the x86 architecture. The PrivUser memory space, a set of pages within process address space that are inaccessible to user mode, is a safe place for application secrets and routines that access them. We implement the LOTRx86 ABI that exports the privcall interface to users to invoke secret handling routines in PrivUser. This way, sensitive application operations that involve the secrets are performed in a strictly controlled manner. The memory access control in our architecture is privilege-based, accessing the protected application secret only requires a change in the privilege, eliminating the need for costly remote procedure calls or change in address space. We evaluated our platform by developing a proof-of-concept LOTRx86-enabled web server that employs our architecture to securely access its private key during an SSL connection. We conducted a set of experiments including a performance measurement on the PoC on both Intel and AMD PCs, and confirmed that LOTRx86 incurs only a limited performance overhead.
Hojoon Lee 0001, Chihyun Song, Brent ByungHoon Kang
CCS2