In today's rapidly evolving technological landscape, Machine Learning (ML) has become an integral part of our daily lives, ranging from recommendation systems to advanced medical diagnostics and autonomous vehicles.As ML continues to advance, its applications extend beyond conventional boundaries.With the continuous refinement of the models and frameworks, the possibilities for leveraging these technologies into devices that traditionally lacked any form of computational autonomy are ever-expanding.This shift towards embedding ML capabilities directly into edge devices brings new challenges due to the stringent limitations these devices have in terms of memory, power consumption, and cost.The ML models implemented on such devices must find an equilibrium between memory footprint and performance, attaining a classification time that fulfills real-time demands and maintains a similar level of accuracy as the desktop version.Without automated assistance in managing these considerations, the complexity of evaluating multiple models can lead to suboptimal decisions.In this paper, we introduce MLino Bench, an open-source benchmarking tool tailored for assessing lightweight ML models on edge devices with limited resources and capabilities.The tool accommodates various models, frameworks, and platforms, presenting a meticulous design that enables a comprehensive evaluation directly on the target device.It encompasses crucial metrics such as on-target accuracy, classification time, and model size, providing a versatile framework that assists practitioners in decision-making when deploying models to such devices.The tool employs a fully streamlined benchmark flow involving training the ML model in a highlevel interpreted language, porting, compiling, flashing, and finally benchmarking on the actual target.Our experimental evaluation of the tool highlights its flexibility in assessing multiple ML models across different model hyperparameters, frameworks, datasets, and embedded platforms.Furthermore, a distinctive advantage compared to state-of-the-art ML benchmarking tools is the inclusion of classical ML models, including Random Forests, Decision Trees, Support Vector Machines, Naive Bayes, and more.This sets our tool apart from others that predominantly emphasize only neural network models.Due to this inclusive approach, our tool facilitates the evaluation of ML models across a broad spectrum of devices, ranging from resource-constrained edge devices to those with medium and advanced computational capabilities.

Photoplethysmography (PPG) is a widely used technique to extract physiological information non-invasively. Besides other factors, the transimpedance amplifier (TIA) topology choice has an impact on the PPG signal. This study presents a novel quantitative evaluation of seven different resistive TIA topologies in terms of four different Signal Quality Indexes (SQIs): AC amplitude, perfusion index, signal shape quality and signal-to-noise-ratio. Results indicate that a differential TIA configuration is preferred over the single-stage and that while the PD polarity has no impact on the PPG signal quality, the bias choice is important, being the zero bias configuration more beneficial than the reverse bias.

Many people in the world are living with chronic diseases, demanding continuous monitoring, diagnosis, and treatment. Continuous physiological monitoring is key to providing preventive healthcare and accurate disease diagnosis, which leads to a growing demand for autonomous wearable technology. Wearable devices acquiring physiological information from the patient demand high-power efficiency to operate in a continuous acquisition mode. While power-saving techniques are applied in wearable devices for many application, very few are considered for biomedical applications. In this work, we explore existing techniques of power reduction for wearable medical devices. Our analysis addresses the power reduction of wearable medical devices and their generalization for different medical signal processing applications. In addition, we propose a taxonomy for power-saving techniques. The common categories of power-saving techniques are task scheduling, clock management, signal compression, and energy awareness. The presented analysis identifies the most appropriate and combined low-power techniques in wearable devices to reduce power consumption.

Off-chip interconnects with a length between 5 and 20 cm can typically be modeled as lumped capacitors for operating speeds up to 50-250 MHz. These capacitors can be driven in such a way that their energy is recycled, reducing the power dissipation. This can be achieved by one or more inductors that are included at the driving side allowing energy transfer from the logic level changing interconnects to the inductors and back. Since most of the energy is recycled, the dissipation for changing logic level is reduced considerably. The method is verified first on circuits designed in 0.5 /spl mu/m CMOS at Vcc=3.3 V, rendering power reduction to 48% of conventional drivers at 10 MHz operating frequency and reduction to 58% at 40 MHz.