Threshold logic is an alternative representation of conventional Boolean logic and re-attracted researchers’ attention in recent years. Previous works have demonstrated that a 2 nd -order threshold logic gate (2-TLG) could have a lower area cost than a 1 st -order TLG (1-TLG) and proposed an integer linear programming (ILP)-based method for identifying 2-TLGs. However, the method could suffer from inefficiency for complex Boolean functions. In this article, we first enhance the ILP-based method for transforming a 1-TLG into a 2-TLG with a lower area cost. We observe that for a 2-TLG, most of the 2 nd -order weights (2-weights) are zero. That is, in the ILP formulation, most of the variables for the 2-weights can be set to zero without quality sacrifice. Thus, to identify the 2-weights that are more likely to be non-zero, we first propose sufficient conditions to derive a 2-TLG from a 1-TLG by extracting 2-weights. We then simplify the ILP formulation by eliminating the non-extracted 2-weights to facilitate the ILP-solving process. Furthermore, we propose a synthesis scheme for 2 nd -order threshold logic based on the enhanced ILP-based method. We leverage the state-of-the-art 1 st -order threshold logic synthesis technique to generate a 1 st -order threshold logic network (1-TLN) first and then transform it into a 2 nd -order TLN (2-TLN). The experimental results demonstrate that when transforming a set of 1-TLGs into 2-TLGs, the enhanced ILP-based method reduces the total CPU time by approximately 31% across all 1-TLGs, with only an average quality loss of 0.07% in terms of the area cost reduction rate. Additionally, when transforming two sets of 1-TLNs with different maximum fanin counts into 2-TLNs, the proposed method achieves average area cost reductions of 8.04% and 22.18%, respectively.

In this article, we present a don’t-care-based threshold logic gate (TLG) minimization method for threshold logic network (TLN) optimization. We first introduce a sufficient condition for the don’t cares of a TLG to exist in a TLN and propose a logic-implication-based method to identify the don’t cares. Then, we present two different methods for minimizing the TLG with the don’t cares. The first one is an integer linear programming (ILP)-based method. We model the minimization problem as an ILP problem and propose an approach to compute the necessary constraints of the ILP formulation. The second one is a heuristic method adapted from a threshold function identification approach. In the experiments, we applied the proposed methods to two sets of TLNs generated by the up-to-date synthesis technique. The results show that, for the two sets of TLNs, the ILP-based method achieves an average of 12% and 23% area reduction without any overhead on the TLG count and logic depth. Furthermore, the heuristic method is more efficient than the ILP-based method with only a little quality loss.

This paper introduces a method to enhance an integer linear programming (ILP)-based method for transforming a 1st-order threshold logic gate (1-TLG) to a 2nd-order TLG (2-TLG) with lower area cost. We observe that for a 2-TLG, most of the 2nd-order weights (2-weights) are zero. That is, in the ILP formulation, most of the variables for the 2-weights could be set to zero. Thus, we first propose three sufficient conditions for transforming a 1-TLG to a 2-TLG by extracting 2-weights. These extracted weights are seen to be more likely non-zero. Then, we simplify the ILP formulation by eliminating the non-extracted 2-weights to speed up the ILP solving. The experimental results show that, to transform a set of 1-TLGs to 2-TLGs, the enhanced method saves an average of 24% CPU time with only an average of 1.87% quality loss in terms of the area cost reduction rate.

Threshold logic re-attracts researchers' attention recently due to the advancement of hardware realization techniques and its applications to deep learning. In the past decade, several design automation techniques for threshold logic have been proposed, such as logic synthesis and logic optimization. Although they are effective, threshold logic network (TLN) optimization based on don't cares has not been well studied. In this paper, we propose a don't-care-based node minimization scheme for TLNs. We first present a sufficient condition for don't cares to exist and a logic-implication-based method to identify the don't cares of a threshold logic gate (TLG). Then, we transform the problem of TLG minimization with don't cares to an integer linear programming problem, and present a method to compute the necessary constraints for the ILP formulation. We apply the proposed optimization scheme to two set of TLNs generated by the state-of-the-art synthesis technique. The experimental results show that, for the two sets, it achieves an average of 11% and 19% of area reduction in terms of the sum of the weights and threshold values without overhead on the TLG count and logic depth. Additionally, it completes the optimization of most TLNs within one minute.

In this article, we present an optimization method for threshold logic networks (TLNs) based on observability don’t-care-based node merging. To reduce gate count in a TLN, it iteratively merges two gates that are functionally equivalent or whose differences are never observed at the primary outputs. Furthermore, it is able to identify redundant wires and replace wires for removing more gates. Basically, the proposed method is primarily adapted from an ATPG-based node-merging approach which works for conventional Boolean logic networks. To extend the approach for TLNs, we develop a method for computing mandatory assignments of a stuck-at fault test on a threshold gate and a method for conducting logic implication in a TLN. Additionally, to achieve a better optimization quality, we integrate the proposed method with other optimization methods. The experimental results show that the overall optimization method can save an average of approximately 4.7% threshold gates for a set of TLNs which are generated by using the latest TLN synthesis method. The experimental results also demonstrate the efficiency of the optimization method.