Chiplet-based systems provide a scalable platform for heterogeneous integration, but permanent faults in interconnects and memory cells challenge their reliability. While standards like Universal Chiplet Interconnect Express (UCIe) employ single-domain system Error Correction Code (ECC) simplify architecture, they often limit fault isolation and recovery. This paper proposes a dual-mode Online Built-In Self-Repair (OBISR) architecture for unified detection and repair of both interconnect and memory faults during post-bond testing and in-field operation. Unlike conventional methods that merely expand ECC capacity, the OBISR targets the root causes of persistent errors by repurposing existing Content-Addressable Memory (CAM) and pathfinding logic. A hierarchical CAM structure classifies faults using spatial and recurrence patterns of ECC metadata to distinguish permanent defects from transients. Memory faults are masked via logical redirection, while interconnect faults are rerouted, both operating outside the datapath to ensure zero performance degradation. Evaluations demonstrate that the OBISR improves system-level resilience by 235.49% and reduces hardware area by 16.69% compared to conventional schemes. Its integrated dual-domain and dual-mode capabilities offer a robust, scalable solution for next-generation chiplet reliability.

In the field of deep learning, has seen significant advancements; however, shadow removal remains a persistent challenge owing to the variable sizes and colors of shadows influenced by lighting conditions. This study proposes a novel shadow-feature refinement network (SFR-Net), which leverages supervised learning, feature refinement loss, and knowledge distillation to enhance shadow removal performance. A dedicated post-processing algorithm is further introduced to restore natural color consistency in the generated shadow-free images. We evaluated our method on two public datasets: the adjusted image shadow triplet dataset (ISTD+) and the shadow removal dataset (SRD), which demonstrate strong generalization capabilities under diverse conditions. On ISTD+, our model achieved a root mean square error (RMSE) of 3.4627 and structural similarity index measure (SSIM) of 0.9382 across the entire image. On SRD, it recorded an RMSE of 4.3781 and an SSIM of 0.9341. These comprehensive results show that our approach performs competitively across both shadow and non-shadow regions while setting a promising direction for robust and perceptually natural shadow removal.

High-bandwidth memory (HBM) is one of the 3-D stacked memory standards that demonstrate high performance, including high bandwidth, large capacity, and low power consumption. However, despite these advantages, issues related to reliability and yield have imposed limitations on mass production. Various methodologies to enhance the reliability of HBM have been proposed, such as built-in self-repair (BISR) architectures and error correction code algorithms. Nevertheless, ensuring the reliability of through-silicon vias (TSV) remains a challenging problem. Existing built-in architectures aiming to enhance TSV reliability often incur significant hardware overhead, limiting practical applications. In this article, an innovative TSV BISR architecture that can detect and repair permanent TSV faults in real time at the user stage is proposed. The proposed architecture significantly enhances the reliability of HBM while implementing it with minimal hardware overhead. Furthermore, it effectively identifies both temporary errors and permanent TSV faults, enabling efficient TSV repairs. Through fast and accurate TSV fault repair, the proposed architecture substantially improves the reliability of HBM.

With advancements in manufacturing and design technology, memory integration density has improved. However, as integration density increases, the cost of testing and repairing memory has also risen, posing a significant challenge in memory production. To address this challenge, built-in self-repair (BISR) has been proposed. Traditional built-in redundancy analysis (BIRAs) performs limited analysis of faults during the fault collection process, resulting in a significant delay in generating a repair solution after the test sequence is completed. This inefficiency arises from the time required to repair the memory posttest. This article proposes a new fast and optimal BIRA using smart potential case collection. The proposed BIRA conducts a detailed analysis of detected faults during the test process. Using this novel fault collection results, a potential case is generated. This is a repair case that can repair the memory with a high probability and is generated immediately after the test sequence ends. If the memory cannot be repaired by the potential case, an exhaustive search is conducted for the faults requiring further analysis to generate an optimal repair solution. Compared to previous studies, the proposed BIRA demonstrates extremely low analysis time with an optimal repair rate.

A voltage-divider-based through-silicon-via (TSV) test architecture tests the TSV by using the voltage value differently divided according to TSV defects. This architecture is widely used for TSV testing owing to its small hardware overhead and high test speed. However, the existing voltage-divider-based TSV test architectures are vulnerable to process–voltage–temperature (PVT) variations and noise. In addition, they cannot effectively detect pinhole defects. This study proposes a novel error-tolerant voltage-divider-based TSV test architecture to address these problems. The proposed architecture reduces the test errors by appropriately adjusting the on-resistance value of each MOSFET and adding a compensator circuit. In addition, it effectively detects the pinhole defects by modifying the voltage divider structure and changing the MOSFET control method. Experimental results reveal that the proposed architecture promptly tests various TSV defects and significantly reduces the test errors.

High-bandwidth memory (HBM) is the latest 3-D-stacked dynamic random access memory (DRAM) standard adopted in Joint Electron Device Engineering Council (JEDEC). It has many advantages, such as high bandwidth, large capacity, and low power consumption, but mass production is challenging due to its low yield and reliability. One of the reasons is that through-silicon-vias (TSVs) are prone to defects. Therefore, HBM requires a TSV built-in self-repair (TBISR) architecture that can repair the TSV at a high repair rate even after chip shipment; however, implementing it through existing TSV repair architectures is difficult. They have a large area overhead or a low repair rate. In addition, they lack consideration for bidirectional TSV repair. To address these issues, this article proposes a novel TBISR architecture that can repair bidirectional TSVs and has a small area overhead and a high repair rate. Experimental results show that the proposed architecture, capable of bidirectional TSV repair, has a high repair rate, despite the small size compared to other architectures.

With technological advancements, the density and capacity of memory are rapidly increasing. As the number of memory cells increases, the difficulty of fault analysis and the number of faults also increase. Hence, the yield and test cost of memory have become essential issues in memory manufacturing. Many manufacturers have used redundancy analysis (RA) to improve the memory yield and decrease the test cost. However, most conventional RA methods require a lengthy analysis time to find a repair solution, and it is difficult to obtain an optimal repair rate with conventional RA algorithms. Although several algorithms using various spare structures to achieve performance improvement have been proposed, those improvements have not been ground breaking. In this article, a new multibank optimized RA (MORA) algorithm is proposed. It achieves a very high repair rate and a drastic reduction in the analysis time compared with conventional RA algorithms using various spare structures. During testing, the proposed algorithm stores the faulty cell information efficiently. Therefore, the analysis time can be shortened through the presolution process of the repair analysis using the proposed fault storage spaces. Additionally, the proposed spare structures are used to increase the repair rate. The experimental results reveal that the proposed algorithm can achieve a very high repair rate at a faster speed than conventional RA algorithms.

Three-dimensional integrated circuits (3-D ICs) utilizing through-silicon via (TSV) technology have many advantages over 2-D ICs, including high bandwidth, high density, and low power consumption. However, TSV, which is a key feature of 3-D ICs, has not only problems due to defects in the manufacturing process but also potential problems due to aging. Various solutions have been proposed to address each of these issues, but no one solution has been proposed considering both. In practice, to improve the overall reliability of the TSV, the two problems should be solved together, not separately. In this article, a new TSV architecture is proposed to cope with both issues. The proposed TSV architecture uses redundant TSVs (RTSVs) to repair faulty TSVs due to manufacturing defects and uses unused RTSVs in this way to solve the aging-related problems. Experimental results show that the proposed architecture achieves similar repair rate with less than 1% difference in less than six clustered faults using smaller hardware overhead, and also shows that unused RTSVs are available with a 98.5% high probability, resulting in a 1.5 times improvement in lifetime.

Since the probability of fault occurrence on memory has increased with the advance of memory density and capacity, memory repairs in wafer-level and package-level are widely used with redundancy analysis (RA) to improve memory yield. However, as the costs for memory repair also have increased in proportion to the memory density and capacity, the repair costs have occupied a significant portion of the total costs. To address the problem, one-time memory repair with wafer-level early repair analysis (W-ERA) for cost reduction is proposed in this paper. The proposed W-ERA facilitates that all unrepairable memories are classified rapidly without searching memory repair solutions in wafer-level and repairable memory faults occurred in wafer-level are repaired in package-level with additional faults occurred in package-level simultaneously. It means, as the costs of memory repair can be highly reduced since memory repair is skipped in wafer-level, the total costs also can be highly reduced. In addition, memory redundancies can be efficiently used for memory repair in package-level and it results a high repair rate achievement.

As advances in memory density and capacity result in an increase in the probability of fault occurrence, many studies on built-in redundancy analysis (BIRA) have been conducted to address this problem. However, conventional BIRAs cannot directly find a final repair solution as soon as test sequences of the built-in self-test (BIST) are over, because they require starting the fault analyses after finishing the test sequences to achieve an optimal repair rate. For this reason, additional analysis time is inevitable, which affects total test costs. In this paper, a dynamic BIRA is proposed for memory repair. It can find a final repair solution directly as soon as test sequences if the BIST are over and achieve an optimal repair rate. The proposed BIRA can restore faults in fault-storing content-addressable memories whenever the spaces in them can be reduced via dynamic fault analysis. Furthermore, the proposed BIRA can be implemented with a reasonable hardware size. This is demonstrated via experiments.

With the development of memory manufacturing technology, the density of memory die has been increased and more data can be stored in a small area than before. However, due to the complexity of the manufacturing process, faults in memory have increased. And it leads to poor yield and quality of memory. To improve yield and quality of the memory, the importance of memory test and repair is growing to maintain memory productivity. This paper presents solutions for test and repair in pre-bond. In the pre-bond, proposed method makes a new 3D stacked memory by using unrepairable memory dice which cannot be repaired with existing spare memories. Discard the bank with the largest number of faults in the unrepairable memory die and repair the remaining banks. The memory dice and a spare layer which made of the known good die or unrepairable memory die are stacked to create a 3D memory. A bank of the spare layer is mapped to discarded bank of unrepairable memory die to operate as one normal working memory die. The proposed method can lead to high yields of 3D stacked memory.