The use of logic circuits combined with emerging devices has been studied to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) transistors. Among a variety of emerging devices, magnetic tunnel junction (MTJ) is a promising candidate owing to its non-volatility, high endurance, and CMOS compatibility. However, process variations in MTJs and CMOS transistors hinder reliable and precise resistance-to-voltage conversion in hybrid MTJ/CMOS logic circuits. To address this issue, this paper proposes a novel separated pre-charge sense amplifier that achieves fast-sensing, low-power, small-area, and high-reliability. The proposed circuit eliminates intermediate inverters between the discharge and evaluation stages. It incorporates P-channel MOS (PMOS) transistors within the inverter latch, whose gates are directly biased by voltages that reflect the resistance difference between a pair of MTJs. It minimizes its nodes to be charged or discharged during operation. Furthermore, it reduces the total transistor count, including clock-driven transistors. Simulations are performed using Cadence and HSPICE tools with the NCSU CMOS 45nm design kit and a physics-based MTJ SPICE model. Monte Carlo simulations are conducted to check the circuit’s reliability under process, voltage, and temperature (PVT) variations. Post-layout simulation results show that the proposed circuit achieves the fastest sensing delay among the compared circuits except for Separated Pre-Charge Sense Amplifier (SPCSA), lowest power consumption, lowest power-delay product, smallest area overhead, and lowest sensing error rate for a viable usage in hybrid MTJ/CMOS logic memory circuits.

This paper proposes a high speed modified Dickson charge pump. The conventional circuit has an auxiliary stage to control the gate of the transistor to the output load. However, the auxiliary stage's voltage level has a problem with a threshold voltage loss due to its diode- connected n-channel metal oxide semiconductor (NMOS) transistor configuration. The proposed circuit demonstrates a scheme with p-channel metal oxide semiconductor (PMOS) transistor configuration instead of the conventional NMOS diode connection in the auxiliary stage. Using this method, the threshold voltage loss is eliminated in the voltage level of the auxiliary stage. The gates of the main transfer transistors are controlled more effectively, leading to the proposed circuit's better performances. The bulk connection of PMOS transistor in the auxiliary stage is also modified to suppress the parasitic bipolar effect. The HSPICE simulations with the TSMC 0.18 μm process technology indicate and verify that the proposed circuit achieves better performances in pump-up speed, output ripple peak-to-peak voltage, and power efficiency compared to those obtained for the conventional schemes.

A bit-line sense amplifier using PMOS charge transfer pre-sensing (CTPS) circuit is proposed. The CTPS circuit using charge sharing operation between lines which have different capacitance is useful for increasing small bit-line voltage differences. The PMOS latch transistors of CTPS circuit are used for pre-sensing operation and pull-up latching operation. Because the PMOS latch transistors are used mutually, area overhead of the CTPS is minimized. The PMOS CTPS circuit increases the small bit-line voltage difference and the output voltage difference of the CTPS circuit becomes the input voltage difference of the latch sense amplifier. Using the PMOS CTPS circuit, the speed of read operation and the reliability of the read operation is improved. The performance of the proposed scheme is verified by the simulation using a 45 nm process.

In this paper, a method is proposed to reduce the write energy consumption in order to reduce the energy consumption of the circuit composed of spin-torque transfer magnetic RAM(STT-MRAM). Of the total energy consumption of the circuit, the write energy consumption occupies a large proportion. Omission of unnecessary write operations increases efficiency in terms of energy consumption. Compare the data to be written with the data to be written before proceeding with the write operation of the circuit to omit the unnecessary write operation and selectively execute the necessary write operation. As the number of MTJ increases, the gain in side of energy can be increased, so the simulation had proceeded by increasing the number of MTJ to 512. Simulation results show that the worst case energy consumption consumes 16.5% more energy than the conventional one, but it can reduce energy consumption by up to 90.6% at best. Reliability also increases through the process of comparing write data (WD) with data stored in MTJ.

A low voltage charge pump with high pumping efficiency is proposed in this paper. To get high pumping efficiency, the proposed circuit uses 2 branches cross coupled structure. To eliminate the body effect and threshold voltage drops, PMOS transistors are used as Charge Transfer Switch (CTS). The inverters below and above the CTS PMOS for controlling the gate of CTS PMOS properly. Undesired charge transfer flows higher voltage node voltage to lower voltage node is removed as the NMOS transistor and PMOS transistor below and above the CTS PMOS turn off during the clock transition. Furthermore, the time when those NMOS transistor and PMOS transistor are both off is short and due to the cross coupled wiring, the fast gate control would be able to made by present and previous stage. So that the cross coupled CTS charge pump has higher pumping efficiency than conventional circuits. The simulation results show that the proposed circuit's performance is better than other circuits.