In industrial settings, the health state of a product is often difficult to observe directly. Instead, it is typically inferred from noisy degradation data that are related to the system’s operational condition. However, existing methods commonly neglect parameter uncertainty and lack the ability to perform real-time state estimation. To address these challenges, this article proposes a Bayesian inference framework for accurate online identification of system degradation states. Specifically, a Wiener process model with measurement noise is developed, and prior distributions are introduced to capture parameter uncertainty. In the offline training stage, historical measurement data are utilized to approximate the joint posterior distribution of the latent degradation states and model parameters via variational Bayesian methods. In the online stage, a state-space formulation is adopted to dynamically update the posterior distribution using real-time observations, enabling dynamic estimation of the degradation state. The proposed approach significantly reduces both storage and computational costs. Numerical simulations and real-world case studies demonstrate that the proposed method achieves superior performance in terms of both accuracy and efficiency.

For many industrial products, accelerated degradation tests (ADTs) serve as an efficient approach to their reliability prediction. Modeling and analyzing the ADT data involves assessing the accelerating effect brought by stress variables, as well as accounting for multiple variation sources. In many situations, in addition to unit-to-unit variabilities seen in both the initial performance levels and degradation rates, an intriguing observation is that these two factors exhibit a strong correlation. Motivated by a real application of optical media, this article proposes a general Wiener process for modeling such ADT data, and it provides a closed-form lifetime distribution. An expectation-maximization algorithm is developed to infer the unknown parameters. An extension to the Bayesian approach under Stan framework is made to enable practitioners to seamlessly incorporate prior domain knowledge into their analysis. Simulation studies and a case application demonstrate the good performance of the proposed methodology.

For routing closures in package designs, net order is critical due to complex design rules and severe wire congestion. However, existing solutions are deliberatively designed using heuristics and are difficult to adapt to different design requirements unless updating the algorithm. This work presents a novel deep learning-based routing framework that can keep improving by accumulating data to accommodate increasingly complex design requirements. Based on the initial routing results, we apply deep learning to concurrent detailed routing to deal with the problem of net ordering decisions. We use multi-agent deep reinforcement learning to learn routing schedules between nets. We regard each net as an agent, which needs to consider the actions of other agents while making pathing decisions to avoid routing conflict. Experimental results on industrial package design show that the proposed framework can improve the number of design rule violations by 99.5% and the wirelength by 2.9% for initial routing.

This article presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry island and monotonic current flow while minimizing wire crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire crossings among critical nets, may increase wire load and performance degradation. This article proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

Conducting accelerated degradation tests (ADTs) is an effective way to assess reliability of highly reliable products. In the existing literature, most works deal with planning ADT with a single stress variable; however, the situation of more than one stress variable is commonly seen in engineering practice. To fill the gap, in this article, we provide an analytical approach to address the design issue when two stress variables are present. By using a linear mixed-effects model to describe the accelerated degradation process, we demonstrate that the design problem can be solved by, first, finding the optimal setting of test conditions and allocation of test units for a “single-variable” case, and then the initial solution is transformed to the test plan for the case of two stress variables. The transformation is done by maintaining the same value of the asymptotic variance of the estimated pth quantile lifetime, along with the consideration of reducing the asymptotic variance of model parameters estimation. We also discuss how to find compromise plans that satisfy practical demands. Finally, the proposed framework is illustrated using a real-world example.

Design flow parameters are of utmost importance to chip design quality and require a painfully long time to evaluate their effects. In reality, flow parameter tuning is usually performed manually based on designers' experience in an ad hoc manner. In this work, we introduce a machine learning-based automatic parameter tuning methodology that aims to find the best design quality with a limited number of trials. Instead of merely plugging in machine learning engines, we develop clustering and approximate sampling techniques for improving tuning efficiency. The feature extraction in this method can reuse knowledge from prior designs. Furthermore, we leverage a state-of-the-art XGBoost model and propose a novel dynamic tree technique to overcome overfitting. Experimental results on benchmark circuits show that our approach achieves 25% improvement in design quality or 37% reduction in sampling cost compared to random forest method, which is the kernel of a highly cited previous work. Our approach is further validated on two industrial designs. By sampling less than 0.02% of possible parameter sets, it reduces area by 1.83% and 1.43% compared to the best solutions hand-tuned by experienced designers.

At the end of digital integrated circuit (IC) design flow, some nets may still be left open due to engineering change order (ECO). Resolving these opens could be quite challenging for some huge nets such as power ground nets because of a large number of obstacles and greatly distributed net components. Existing studies on multilayer obstacle-avoiding rectilinear Steiner trees may not be applicable to solve this problem because they assume the pins of an input net is a set of points, while the discrete net components in this problem can be regarded as a set of rectilinear pins. In this paper, we develop an efficient open-net connector that can deal with rectilinear pins. The proposed algorithm flow minimizes the total connection cost based on precise estimation of the shortest distance between each pair of rectilinear net components with the presence of complex obstacles. The experimental results show that the proposed flow can outperform the top-three teams of 2017 CAD contest at ICCAD and a state-of-the-art work in terms of total connection cost or runtime efficiency.

With the dramatic shrink of feature size and the advance of semiconductor technology nodes, numerous and complicated design rules need to be followed, and a chip design can only be taped-out after passing design rule check (DRC). The high design complexity seriously deteriorates design routability, which can be measured by the number of DRC violations after the detailed routing stage. In addition, a modern large-scaled design typically consists of many huge macros due to the wide use of intellectual properties (IPs). Empirically, the placement of these macros greatly determines routability, while there exists no effective cost metric to directly evaluate a macro placement because of the extremely high complexity and unpredictability of cell placement and routing. In this paper, we propose the first work of routability-driven macro placement with deep learning. A convolutional neural network (CNN)-based routability prediction model is proposed and embedded into a macro placer such that a good macro placement with minimized DRC violations can be derived through a simulated annealing (SA) optimization process. Experimental results show the accuracy of the predictor and the effectiveness of the macro placer.

At the end of digital integrated circuit (IC) design flow, some nets may still be left open due to engineering change order (ECO). Resolving these opens could be quite challenging for some huge nets such as power ground nets because of a large number of obstacles and greatly distributed net components. Existing studies on multilayer obstacle-avoiding rectilinear Steiner trees may not be applicable to solve this problem because they assume the pins of an input net is a set of points, while the discrete net components in this problem can be regarded as a set of rectilinear pins. In this paper, we develop an efficient open-net connector that can deal with rectilinear pins. The proposed algorithm flow minimizes the total connection cost based on precise estimation of the shortest distance between each pair of rectilinear net components with the presence of complex obstacles. Experimental results show that the proposed flow can outperform the top three teams of 2017 CAD Contest at ICCAD in terms of total connection cost or runtime efficiency.

Early routability prediction helps designers and tools perform preventive measures so that design rule violations can be avoided in a proactive manner. However, it is a huge challenge to have a predictor that is both accurate and fast. In this work, we study how to leverage convolutional neural network to address this challenge. The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots. In both cases, large macros in mixed-size designs are taken into consideration. Experiments on benchmark circuits show that RouteNet can forecast overall routability with accuracy similar to that of global router while using substantially less runtime. For DRC hotspot prediction, RouteNet improves accuracy by 50% compared to global routing. It also significantly outperforms other machine learning approaches such as support vector machine and logistic regression.