Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.

As Engineering Change Order (ECO) has attracted substantial attention in modern VLSI design, the open net problem, which aims at constructing a shortest obstacle-avoiding path to reconnect the net shapes in an open net, becomes more critical in the ECO stage. This paper addresses a multi-layer obstacle-avoiding region-to-region Steiner minimal tree (SMT) construction problem that connects all net shapes by edges on a layer or vias between layers, and avoids running through any obstacle with a minimal total cost. Existing multi-layer obstacle-avoiding SMT algorithms consider pin-to-pin connections instead of region-to-region ones, which would limit the solution quality due to its lacking region information. In this paper, we present an efficient algorithm based on our new multi-layer obstacle-avoiding region-to-region spanning graph to solve the addressed problem, which guarantees to find an optimal solution for a net connecting two regions on a single layer. Experimental results show that our algorithm outperforms all the participating routers of the 2017 CAD Contest at ICCAD in both solution quality and runtime.

Among many asynchronous design styles, precharge half/full buffers (PCHB/PCFB) are popular due to small area and high performance. This paper proposes new test methodology for PCHB/PCFB asynchronous circuits. Our proposed design for testability (DfT) does not break any internal feedback loop so it is small in area. There are two major theoretical contributions in this paper. First, this paper analyzes the fault effects of transition delay faults, which were not studied in depth by previous research. Second, we also analyze faults on fanout branches that break the isochronic fork assumption. One important conclusion is that these faults can not only degrade the circuit performance but also modify data so they must be tested. We propose three-pattern tests for stuck-at faults and four-pattern tests for transition delay faults. In addition, we propose a new model for ATPG so that existing tools can be used. On the average, our work achieves 93% and 92% stuck-at and transition delay fault coverage, respectively, which is much higher than previous techniques.