Jiaona Zhou

dblp:221/2874 · DBLP profile ↗
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4ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Storage systems · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
1.542021
An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime · DAC 2019
WARD: Wear Aware RAID Design Within SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Storage systems › flash and SSD › flash memory management
garbage collection
0.932021
An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs · DAC 2018
WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime · DAC 2019
Storage systems › flash and SSD › flash memory management
wear leveling
0.922021
An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime · DAC 2019
Storage systems
storage reliability
0.722018
WARD: Wear Aware RAID Design Within SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs · DAC 2018
Storage systems › flash and SSD
SSD RAID
0.312018
WARD: Wear Aware RAID Design Within SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Storage systems
data migration
0.112021
An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021

Methods — techniques the papers use, named apart from their topics

copyback · 0.5SSDsim simulation · 0.5wear-aware superblock organization · 0.4simulation · 0.3data migration · 0.3block wear detection · 0.3RAID stripe reorganization · 0.3
YearPublicationVenuePosition
2021 An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs
abstract
Garbage collection (GC) is time consuming and frequently executed all over the lifetime of solid-state drives (SSDs), which has a significant impact on system performance. Manufactures provide the copyback that directly transfers data within the same plane to accelerate data migration in GC. However, the introduction of copyback leads to two issues: 1) high detection overhead of copyback feasibility (whether data are carried out via copyback with guaranteed reliability) and 2) interplane unbalanced wear distribution. In this article, we first explore copyback error characteristics on the real NAND flash chip, then propose a fast GC scheme called FastGC. It utilizes copyback error characteristics to efficiently detect the copyback feasibility of data instead of transferring out all valid data for detecting. FastGC further utilizes a data migration leveler which aims at relieving migration overhead per GC to realize the wear leveling. Regarding data migrated via external data move (EDM), FastGC takes data coldness and erase counts of planes into consideration to even out the number of migrating data per plane and prolong the lifetime of SSDs. SSDsim, a validate simulation is used to implement FastGC and comprehensive experiments are carried out with various enterprise workloads to evaluate the system performance and the wear difference of SSDs. The experimental results in the SSDsim show the FastGC greatly promotes system performance and the wear leveling up to 46.68% and 12X, respectively, compared to the traditional copyback-based GC.
Shunzhuo Wang, You Zhou 0009, Jiaona Zhou, Fei Wu 0005, Changsheng Xie 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2019 WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime
abstract
Superblocks are widely employed in SSDs for improving performance. However, the standard superblock organization which links blocks with the same block ID across planes into one superblock leads to SSDs' ineluctable lifetime waste due to inter-block wear tolerance variations. This work proposes a wear-aware superblock management, called WAS, which (1) dynamically organizes superblocks according to real-time block wear levels to make strong blocks relieve wear on weak ones, and (2) employs a wear-based garbage collection scheme to reduce inter-block wear gap. Comprehensive experiments are carried out in SSDsim. Results show that WAS greatly prolongs SSD lifetime by 51.3% compared with the state-of-the-art superblock management.
Shunzhuo Wang, Fei Wu 0005, Chengmo Yang, Jiaona Zhou, Changsheng Xie 0001, Jiguang Wan 0001
DAC4
2018 FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs
abstract
Copyback is an advanced command contributing to accelerating data migration in garbage collection (GC). Unfortunately, detecting copyback feasibility (whether copyback can be carried out with assurable reliability) against data corruption in the traditional copyback-based GC causes an expensive performance penalty. This paper first explores copyback error characteristics on real NAND flash chips, then proposes a fast garbage collection scheme called FastGC. It utilizes copyback error characteristics to efficiently detect copyback feasibility of data instead of transferring out all valid data for detecting. Experiment results in the SSDsim show the proposed FastGC greatly promotes write response time and read response time by up to 44.2% and 66.3% respectively, compared to the traditional copyback-based GC.
Fei Wu 0005, Jiaona Zhou, Shunzhuo Wang, Yajuan Du, Chengmo Yang, Changsheng Xie 0001
DAC2
2018 WARD: Wear Aware RAID Design Within SSDs
abstract
Redundant arrays of independent disk (RAID) is an efficient approach to relieve reliability sacrifice caused by aggressive scale-out of solid state drives (SSDs). Unfortunately, RAID is unfriendly to SSDs due to redundant parity write and data rebuilding. This paper proposes a wear aware RAID design for SSDs, called WARD, which: 1) adaptively organizes RAID stripes according to real-time interblock unbalanced wear for relieving high performance and storage overhead caused by parity data and 2) migrates blocks about to break in advance and leaves these blocks unused to reduce data rebuilding overhead. An efficient block wear detection scheme is employed to detect block wear during the whole lifetime of SSDs. Beginning with a large stripe width RAID instead of the redundant worst-case RAID, WARD reorganizes RAID stripes once wear blocks with high bit error rates come out. WARD divides the original stripe into several short width RAID stripes according to the number of wear blocks and separates all wear blocks into different stripes. This not only reduces parity redundancy but also provides high reliability to avoid more than RAID recoverable error-prone chunks remaining in one stripe. For high wear blocks tending to wear-out, data in them are migrated in advance and then the blocks are left unused, which efficiently avoids performance shock caused by data rebuilding. A reliability model considering interblock unbalanced wear is proposed and reveals that WARD provides a high and stable reliability and greatly prolongs the lifetime of SSDs. Comprehensive experiments based on an SSDsim derivative simulator are carried out and experiment results show that WARD considerably improves system performance compared to the worst-case RAID.
Shunzhuo Wang, Fei Wu 0005, Zhonghai Lu, Jiaona Zhou, Changsheng Xie 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4