Demo Data from EDBT 2026 / reviewers in the wild / expert
Varun Bhat
dblp:221/2880
· DBLP profile ↗
3ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
2 papers |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Interconnection networks and networks-on-chip · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip
optical network-on-chip |
0.8 | 2 | 2021 | Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021 SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures · DAC 2018 |
Hardware security and side channels
hardware trojan |
0.5 | 1 | 2021 | Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021 |
Hardware security and side channels › hardware trojan
hardware trojan attacks |
0.3 | 1 | 2018 | SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures · DAC 2018 |
Methods — techniques the papers use, named apart from their topics
process variation based authentication signatures · 0.7architecture-level enhancements · 0.7dense-wavelength-division multiplexing · 0.5dense wavelength division multiplexing · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping AttacksabstractThe compact size and high wavelength-selectivity of microring resonators (MRs) enable photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing (DWDM) in their photonic waveguides, and as a result, attain high bandwidth on-chip data transfers. Unfortunately, a hardware Trojan (HT) in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide, which introduces a serious security threat. This article presents a framework that utilizes process variation-based authentication signatures along with architecture-level enhancements to protect against data-snooping HT during unicast as well as multicast transfers in PNoCs. The evaluation results indicate that our framework can improve hardware security across various PNoC architectures with minimal overheads of up to 14.2% in average latency and of up to 14.6% in energy-delay-product (EDP). Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha, Sairam Sri Vatsavai, Varun Bhat |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 2018 | SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architecturesabstractPhotonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wave-length-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA† that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDM-based PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP). Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha |
DAC | 3 |
| 2018 | Securing Photonic NoC Architectures from Hardware TrojansabstractThe compact size and high wavelength selectivity of microring resonators (MRs) enable photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing (DWDM) in photonic waveguides to attain high bandwidth on-chip data transfers. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a framework that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoCs from data-snooping Hardware Trojans. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDM-based PNoCs with minimal overheads of up to 17.3% in average latency and of up to 15.2% in energy-delay-product (EDP). Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat |
NOCS | 4 |