Demo Data from EDBT 2026 / reviewers in the wild / expert
Andrew Zigerelli
dblp:221/2890
· DBLP profile ↗
4ranked-venue papers
0as first author
2since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 since 2021Security and privacy · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 80% Network security · 20% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
GPUs and heterogeneous computing · 80% Processor architecture and microarchitecture · 13% Memory systems · 7% |
Topics — the 10 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU sharing |
0.8 | 2 | 2020 | A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 PEP: proactive checkpointing for efficient preemption on GPUs · DAC 2018 |
Hardware security and side channels › microarchitectural attacks
cache attacks |
0.6 | 1 | 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks · SP 2022 |
Network security
covert channel |
0.6 | 1 | 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks · SP 2022 |
Hardware security and side channels
microarchitectural side channel |
0.6 | 1 | 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks · SP 2022 |
Hardware security and side channels › microarchitectural attacks
prefetch attacks |
0.6 | 1 | 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks · SP 2022 |
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.6 | 1 | 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks · SP 2022 |
GPUs and heterogeneous computing › GPU sharing
GPU preemption |
0.4 | 1 | 2020 | A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Processor architecture and microarchitecture › multithreading
context switching |
0.3 | 1 | 2018 | PEP: proactive checkpointing for efficient preemption on GPUs · DAC 2018 |
GPUs and heterogeneous computing
preemption |
0.3 | 1 | 2018 | PEP: proactive checkpointing for efficient preemption on GPUs · DAC 2018 |
Memory systems
cache coherence |
0.2 | 1 | 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks · SP 2022 |
Methods — techniques the papers use, named apart from their topics
checkpointing · 0.8prediction scheme · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Adversarial Prefetch: New Cross-Core Cache Side Channel AttacksabstractModern x86 processors have many prefetch instructions that can be used by programmers to boost performance. However, these instructions may also cause security problems. In particular, we found that on Intel processors, there are two security flaws in the implementation of PREFETCHW, an instruction for accelerating future writes. First, this instruction can execute on data with read-only permission. Second, the execution time of this instruction leaks the current coherence state of the target data. Based on these two design issues, we build two cross-core private cache attacks that work with both inclusive and non-inclusive LLCs, named Prefetch+Reload and Prefetch+Prefetch. We demonstrate the significance of our attacks in different scenarios. First, in the covert channel case, Prefetch+Reload and Prefetch+Prefetch achieve 782 KB/s and 822 KB/s channel capacities, when using only one shared cache line between the sender and receiver, the largest-to-date single-line capacities for CPU cache covert channels. Further, in the side channel case, our attacks can monitor the access pattern of the victim on the same processor, with almost zero error rate. We show that they can be used to leak private information of real-world applications such as cryptographic keys. Finally, our attacks can be used in transient execution attacks in order to leak more secrets within the transient window than prior work. From the experimental results, our attacks allow leaking about 2 times as many secret bytes, compared to Flush+Reload, which is widely used in transient execution attacks. Yanan Guo 0002, Andrew Zigerelli, Youtao Zhang, Jun Yang 0002 |
SP | 2 |
| 2021 | IVcache: Defending Cache Side Channel Attacks via Invisible AccessesabstractThe sharing of last-level cache (LLC) among different CPU cores makes cache vulnerable to side channel attacks. An attacker can get private information about co-running applications (victims) by monitoring their accesses in LLC. Cache side channel attacks can be mitigated by partitioning cache between the victim and attacker. However, previous partition works either make weak assumptions about the attacker's strength or force their security mechanisms and thus overhead to every user on the system, regardless of their security requirement. Yanan Guo 0002, Andrew Zigerelli, Youtao Zhang, Jun Yang 0002 |
ACM Great Lakes Symposium on VLSI | 2 |
| 2020 | A Dynamic and Proactive GPU Preemption Mechanism Using CheckpointingabstractThe demand for multitasking GPUs increases whenever the GPU may be shared by multiple applications, either spatially or temporally. This requires that GPUs can be preempted and switch context to a new application while already executing one. Unlike CPUs, context switching in GPUs is prohibitively expensive due to the large context states to swap out. There have been a number of efforts on reducing the overhead of preemption, through reducing the context sizes or overlapping context switching with execution. All those techniques are reactive approaches, meaning that context switching occurs when the preemption request arrives. In this paper, we propose a dynamic and proactive mechanism to reduce the latency of preemption. We observe that kernel execution is almost always preceded by known commands in both CUDA and OpenCL implementations. Hence, a preemption can be anticipated before the actual request arrives. We study such lead time and develop a prediction scheme to perform an early state saving. When the actual preemption is invoked, an incremental update relative to the previous saved state is performed, much like the conventional checkpointing mechanism. Our design can also choose to drain or checkpointing dynamically and accurately according to the feature of kernels in the runtime. This design effectively reduces the stall time of the preempting kernel due to context switching by 58.6%. Moreover, through careful handling of the saved state, we can also reduce the overall size of saved state by an average of 23.3%, compared with a full context switching. Chen Li 0015, Andrew Zigerelli, Jun Yang 0002, Youtao Zhang, Sheng Ma, Yang Guo 0003 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2018 | PEP: proactive checkpointing for efficient preemption on GPUsabstractThe demand for multitasking GPUs increases whenever the GPU may be shared by multiple applications, either spatially or temporally. This requires that GPUs can be preempted and switch context to a new application while already executing one. Unlike CPUs, context switching in GPUs is prohibitively expensive due to the large context states to swap out. There have been a number of efforts on reducing the overhead of preemption, through reducing the context sizes or overlapping context switching with execution. All those techniques are reactive approaches, meaning that context switching occurs when the preemption request arrives. Chen Li 0015, Andrew Zigerelli, Jun Yang 0002, Yang Guo 0003 |
DAC | 2 |