A model that utilizes a graph neural network (GNN) is proposed to estimate wirelength in the early stages of physical design. The model predicts the post-routing wirelength of a net, which addresses the limitations of current estimators including half-perimeter wirelength (HPWL) that tend to under-estimate the true post-routed wirelength of complex nets. Utilizing a dataset of 18 benchmark circuits, the GNN achieves an average R2of 0.825, outperforming HPWL, which yields an R2of 0.764. The GNN demonstrates consistent performance across nets of varying lengths, providing significantly improved accuracy over HPWL for long and multi-path nets. The GNN model is differentiable and compatible with gradient-based optimization methods, while providing an 8× improvement in inference time.

The growing complexity of very large-scale integrated (VLSI) circuits due to CMOS technology scaling has led to an increased interest in utilizing machine learning (ML) techniques for design automation. However, the lack of available datasets and established standards for the representation of datasets presents substantial challenges within the research community. Of particular concern is the lack of interoperability and comparability of ML-driven research in the design of digital circuits, which effectively limits collaboration. In this paper, EDA-schema, an open and comprehensive graph schema, is introduced to address such challenges by providing a structured framework for representing datasets for digital design automation. The schema represents the physical attributes and quality-of-results (QoR) metrics of a circuit across various stages of the physical design flow, including logical synthesis, floorplanning, placement, clock network synthesis, and global and local routing. Utilizing the Skywater 130 nm process design kit (PDK) and the OpenROAD toolset, a dataset of physical designs is generated and analyzed based on the circuits from the IWLS’05 benchmark suite. The dataset is made publicly available, anticipating contributions that further advance the field of ML-driven digital design.

With the recent introduction of techniques to restrict scan chain access, a new class of deobfuscation problems emerge, in which the threat model, although similar to deobfuscation of a logic locked circuit, forms a novel class of attack. In this paper, the concept of a logic restricted circuit is generalized and defined. Next, a novel type of SAT-based attack is proposed for the new class of deobfuscation problems, described as a 2-stage SAT-attack. A SAT-attack resilience measure is developed to quantify the security strength of a logic restricted circuit against a SAT-based attack. Finally, the proposed SAT-resilience framework is applied to compare and evaluate effectiveness of example logic restriction schemes.

In this paper, a metric based on mathematical modeling is proposed to evaluate the strength in security of a logic-locked circuit against a satisfiability (SAT) based attack. Current approaches estimate the SAT resilience experimentally based on time-to-solve or the number of calls to a SAT-solver. However, the estimate is often based on one sample or a small sample size. Due to the possible variation in the search path length of the SAT-attack, a measure of resilience based on statistical characterization is proposed. A probabilistic model of a SAT-attack search process is developed to properly capture the variation in the path length and report the SAT resilience as an expectation of the computational complexity. An estimator of the expected complexity, assuming an equally likely branching probability, is proposed. The model and the estimator allow for 1) the derivation of a closed-form estimate of the expected security, and 2) characterization of the key search space without experimental bias toward SAT-attack implementation or circuit topology. As a case study, an analysis of the security gain per inserted key gate is performed on a full adder circuit. The study reveals a monotonically increasing resilience and provides insights on the most efficient key gate placement strategy that maximizes the achievable security.