This paper presents the circuit design of a two-stage dynamic comparator optimized for high-speed, high-resolution analog-to-digital converters (ADCs). A conventional double-tail comparator is used as a reference for benchmarking. The proposed comparator is implemented using a 28 nm CMOS process and simulated using the Spectre circuit simulator under a 1 V supply. Theoretical analysis and simulation results prove that the proposed circuit is faster compared to the conventional double-tail comparator, while mantaining the same power consumption. Additionally, the design exhibits reduced noise levels, with an RMS noise voltage of less than 100 μV, making it suitable for low-noise applications. In terms of the Figure-of-Merit (FoM), the proposed comparator achieves 128 μW mV2GHz−1, showing a competitive performance compared to other state-of-the-art designs in the literature. These results highlight the effectiveness of the proposed comparator in applications requiring high-speed, low-power, and low-noise ADCs in advanced CMOS technology nodes.

This paper presents a mixed-signal Silicon Photomultiplier with integrated front-end, including a reconfigurable Pulse Shaper. Each Silicon Photon Avalanche Diode of the msSiPM converts a photon into a programmable current pulse. Then, all analog current signals are collected by a transimpedance amplifier which provides an output voltage proportional to the number of triggered SPADs. By properly tuning the shape of the current pulses, the proposed msSiPM rejects the background light and optimizes the Signal-to-Noise Ratio. As the architecture is mostly digital, msSiPM consumes a low static power consumption, equal to 428$\mu $W. The receiver is composed by a$20 \,\, \times 20$-pixel array, and it is fabricated in a 0.11$\mu $m CMOS technology reaching a pixel fill factor equal to 32.8%. Measurements have been carried out under different background photon fluxes, one stronger and one weaker, corresponding to 4.15 and 2.15 GPhotons/s at the SiPM, demonstrating strong background rejection in both conditions. In addition, a SNR maximization has been verified. Analytical models for SNR and Signal-to-Background Ratio have been presented, showing a good matching with experimental results.

This paper presents a performance analysis of a system for electrochemical impedance spectroscopy (EIS). The system, composed by an analog front-end (AFE) and a custom microcontroller (MCU) board, performs the impulse response (IR) measurement of linear and time-invariant (LTI) systems with pseudo-random excitation signals. As a novelty, a specific AFE for the interfacing of two-terminal resistive and capacitive sensors is covered in detail. The paper proposes, for the first time, a mathematical model to predict the impact of the main noise sources in the measured IR. Thanks to the proposed approach, the AFE and the system’s parameters can be properly designed in order to reduce the error, thus, minimizing the energy-per-error figure of merit (FOM) as well. The AFE is realized as discrete-components circuit and it has been included in a custom MCU-based measurement system as an expansion module. The predicted results from the mathematical model, in terms of noise power, SNR, and measurement error are validated through system-level simulation and experimental measurements. The system performs the IR measurement with 1023 points, showing root-mean-square (RMS) measurement errors of 1% and 1.4% for the tested ADC sampling frequencies of 62.5 kHz and 125 kHz, respectively. These lead to excellent FOM values of 128.9 mJ$\cdot $%2and 252.6 mJ$\cdot $%2that outstand the state of the art.

An energy-efficient, wide dynamic-range (DR) CMOS analog front-end (AFE) for chemiresistive sensors is presented. The circuit is specifically designed for the Metal Oxide (MOX) gas sensors, a special technology of chemiresistive sensors, broadly diffused in modern portable devices due to their low-cost and simplicity of use. Energy efficiency is mandatory for the AFE in order to prolong the battery life that supply these devices. The proposed circuit implements the resistance-to-time (R-to-T) conversion of the sensor's resistance by adopting a relaxation oscillator-based architecture. A limiting resistor in series with the sensor is introduced for reducing the circuit's energy-per-measurement (EpM), while mitigating the error due to the sensor's parasitic capacitance. The analysis of the circuit is presented with emphasis on the design trade-off between error due to the sensor's parasitic capacitance and power consumption on one side and read-out sensitivity on the other. The chip prototype is realized in AMS 0.35μm process and has been tested in the DR between 100Ω and 4.7MΩ with an accuracy less than 0.1% and a precision less than 0.029%. The efficacy of the presented AFE is proved by adopting the circuit in a real chemical environment with a commercial sensor. The proposed AFE shows a maximum EpM of 296nJ which is three times better than the state of the art.