This article presents a 26–32-GHz 6-bit bidirectional passive vector modulation phase shifter (PVM-PS) in 40-nm CMOS for phased array systems. The passive phase shifter comprises a center-tap transformer-based quadrature generator/combiner, two 6-bit X-type attenuators, and a differential Wilkinson power combiner/divider. The symmetric design enables bidirectional signal propagation and offers flexible system configuration. Passive switches are sized to optimize the tradeoff among gain variation, insertion loss, and linearity. The phase shifter implemented in 40 nm covers a range of 360° with 5.625° resolution and the rms phase error is between 0.4° and 1.3°. It exhibits <1-dB magnitude imbalance and <1.2° phase imbalance between forward and reverse propagation modes. Its OP1dB is above −1 dBm across the operation frequency.

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies$220\times 630\,\,\mu \text{m}^{2}$and has no power consumption.

This paper presents a fully-integrated 76-81 GHz four-channel digitally controlled receiver (RX) in 65-nm CMOS, which utilizes a four-channel RX front-end with high linearity, an LO distribution network, and a reconfigurable 4-channel analog baseband (ABB). It achieves high integration level and is capable of flexible reconfigurability automotive radars with wide and flattened temperature characteristic. Each RX front-end consists of a low noise amplifier (LNA) employing a neutralized common source (CS) with configurable high-linearity and an active mixer with linearity-priority design. Additionally, a bias circuit with positive temperature coefficient is used for temperature compensation of the millimeter wave (mm-Wave) amplifiers and mixer. The RX chain offers tunable gain and bandwidth (BW) with digital control and bandwidth tuning for the ABB. The measured results show that the RX achieves an input 1-dB compression point (Pin,1dB) of -7 dBm and a noise figure of 11-26 dB across a temperature range from -45 to +125°C, both over the range of 76-81 GHz. The RX has a tunable gain from 18 to 66 dB over the 3-dB programmable IF BW from 0.1 to 10 MHz. The power consumption of the entire receiver is 0.52 W.

This paper presents a 77 GHz Receiver (Rx) for automotive radar with high linearity, low noise figure (NF) and reconfigurable gain and bandwidth of the analog baseband (ABB), implemented in TSMC 65 nm CMOS general purpose (GP) technology. The Rx includes a low-noise amplifier (LNA), sharing the transconductance stage with a double-balanced mixer, an LO chain with a frequency doubler and an analog baseband. The entire Rx consumes 123 mW. Measurement results show that the input 1 dB compression point (P1dB) is -14 dBm at 81 GHz, a conversion gain (CG) of 20.5-62.5 dB is digitally tunable at 77 GHz, and an NF of 11.2-18.3 dB is achieved over the frequency range of 76-81 GHz.