Mission-critical IoT applications in sixth-generation (6G) networks demand decoding error probability of 10−9, latency under 1 ms, and quantum-resistant security. This paper proposesQFL-SecEdge, a quantum federated learning framework integrating post-quantum cryptography for secure, ultra-reliable task distribution in 6G edge computing. QFL-SecEdge features a three-tier architecture comprising: Variational Quantum Circuit-enhanced Federated Deep Reinforcement Learning (VQC-FDRL) with 45% faster convergence; a Lattice-based Post-Quantum Cryptographic (LPQC) layer using CRYSTALS-Kyber with 78% reduced overhead; and an Extreme Value Theory-driven Reliability Assurance (EVT-RA) mechanism guaranteeing 99.99999% reliability. Simulations demonstrate 52% energy efficiency improvement, 38% latency reduction, 10−9decoding error probability, and quantum-resistant security at only 1.3× computational overhead. The reported gains are based on simulation using quantum circuit emulation, simulated 6G IoT devices, and software-based Kyber implementation; results may vary under real-world deployment conditions.

This study is motivated by the growing need for resilient and energy-aware Unmanned Aerial Vehicles-Reconfigurable Intelligent Surfaces (UAV-RIS) systems in 6G IoT environments where dynamic obstacles and mobility hinder connectivity. The framework uniquely integrates hierarchical deep reinforcement learning (DRL), MetaBeam for adaptive beamforming, and federated DRL for decentralized optimization. This paper presents Dynamic Reconfigurable Aerial Governance and Optimization Network (DRAGON), a novel 6G framework that integrates Unmanned Aerial Vehicles (UAVs) and Reconfigurable Intelligent Surfaces (RIS) for enhanced IoT connectivity. Using a hierarchical DRL approach, DRAGON dynamically optimizes UAV trajectories and RIS configurations to adapt to changing network conditions. Simulations show 37% higher energy efficiency, 52% improved data rates, and 28% more IoT device admissions compared to Proximal Policy Optimization - Probabilistic (P-PPO), Centralized Deep Deterministic Policy Gradient (C-DDPG), and Multi-Policy Training (MPT). DRAGON supports RIS densities of 64-256, UAV fleets of 4 to 16 drones, and sub-second deployment latency, proving its scalability and effectiveness in dense, dynamic 6G environments.

Human emotions are intricate psychological phenomena that reflect an individual’s current physiological and psychological state. Emotions have a pronounced influence on human behavior, cognition, communication, and decision-making. However, current emotion recognition methods often suffer from suboptimal performance and limited scalability in practical applications. To solve this problem, a novel electroencephalogram (EEG) emotion recognition network named VG-DOCoT is proposed, which is based on depthwise over-parameterized convolutional (DO-Conv), transformer, and variational automatic encoder-generative adversarial network (VAE-GAN) structures. Specifically, the differential entropy (DE) can be extracted from EEG signals to create mappings into the temporal, spatial, and frequency information in preprocessing. To enhance the training data, VAE-GAN is employed for data augmentation. A novel convolution module DO-Conv is used to replace the traditional convolution layer to improve the network. A transformer structure is introduced into the network framework to reveal the global dependencies from EEG signals. Using the proposed model, a binary classification on the DEAP dataset is carried out, which achieves an accuracy of 92.52% for arousal and 92.27% for valence. Next, a ternary classification is conducted on SEED, which classifies neutral, positive, and negative emotions; an impressive average prediction accuracy of 93.77% is obtained. The proposed method significantly improves the accuracy for EEG-based emotion recognition.

This article introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in the 180-nm CMOS technology. The LP-NGD circuit is an inductorless topology constituted by RC-network with CMOS metal-insulator-metal (MIM) capacitor and polygate resistor. The design methodology is illustrated by considering the chip layout process. Then, the first run simulation is performed with the design rule check (DRC) and 2.5 mm${\times }$2.2 mm layout versus schematic (LVS) approaches. The feasibility of the CMOS LP-NGD IC circuit implementation is validated with chip-onboard (CoB). The proof of concept (PoC) of the LP-NGD miniaturized circuit was tested in both S-parameter and time domain (TD). As expected, the calculated, simulated, and experimented results of CoB showing NGD of about −10 ns over 12 MHz and −10 dB attenuation are confirmed. The active CMOS LP-NGD technology compensates the insertion loss to 2.4 dB, the GD reaches −11 ns, and the reflection loss reaches −20 dB. Moreover, TD investigations were also performed to show the feasibility of generating pulse and arbitrary waveform signal time advance through the designed and fabricated LP-NGD CoB prototypes.

In this paper a new technique for designing finite state machines with concurrent error detection is presented using convolutional codes. In order to correct the fault, we propose a novel scheme which can not only detect but also correct errors occurred in FSM transition. More specifically, we demonstrate how the checker using maximum likelihood decoding can correct single-bit error and get 3dB higher of asymptotic coding gain than previous techniques, also we analysis bit error rate performance for Viterbi decoding of convolutional code. Moreover, we realize the IP core of the self-checking module by SMIC 0.25 mum CMOS technology and also simulate its function in FPGA .