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John Mixter

dblp:222/6872 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 70% Reconfigurable computing and FPGAs · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA-based emulation
0.512021
RANC: Reconfigurable Architecture for Neuromorphic Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Emerging computing paradigms
neuromorphic computing
0.512021
RANC: Reconfigurable Architecture for Neuromorphic Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Emerging computing paradigms › neuromorphic computing
spiking neural network
0.512021
RANC: Reconfigurable Architecture for Neuromorphic Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Emerging computing paradigms
neuromorphic hardware
0.112021
RANC: Reconfigurable Architecture for Neuromorphic Computing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021

Methods — techniques the papers use, named apart from their topics

c++ simulation · 0.5FPGA emulation · 0.5
YearPublicationVenuePosition
2021 RANC: Reconfigurable Architecture for Neuromorphic Computing
abstract
Neuromorphic architectures have been introduced as platforms for energy-efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from nonmachine learning application domains. In order to lift the barriers to entry for hardware designers and application developers, we present RANC: a reconfigurable architecture for neuromorphic computing, an opensource highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of IBM’s TrueNorth and validate with a direct comparison to IBM’s Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of synthetic aperture radar classification and vector matrix multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.
Joshua Mack, Ruben Purdy, Kris Rockowitz, Michael Inouye, Edward Richter, Spencer Valancius, Nirmal Kumbhare, Md Sahil Hassan, Kaitlin Lindsay Fair, John Mixter, Ali Akoglu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.10
2018 Balancing the learning ability and memory demand of a perceptron-based dynamically trainable neural network
Edward Richter, Spencer Valancius, Josiah McClanahan, John Mixter, Ali Akoglu
J. Supercomput.4