EDBT 2026 Demo / reviewers in the wild / expert
Mark S. Neubauer
dblp:223/1854
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0001-8434-9274ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | hls4ml: A Flexible, Open Source Platform for Deep Learning Acceleration on Reconfigurable HardwareabstractWe present hls4ml , a free and open source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this article, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results. Jan-Frederik Schulte, Benjamin Ramhorst, Jovan Mitrevski, Nicolò Ghielmetti, Enrico Lupi, Dimitrios Danopoulos, Vladimir Loncar, Javier M. Duarte, David Burnette, Lauri Laatu, Stylianos Tzelepis, Konstantinos Axiotis, Quentin Berthet, Haoyan Wang, Suleyman Demirsoy, Marco Colombo, Thea Aarrestad, Sioni Summers, Maurizio Pierini, Giuseppe Di Guglielmo, Jennifer Ngadiuba, Javier Campos, Benjamin Hawks, Abhijith Gandrakota, Farah Fahim, George A. Constantinides, Zhiqiang Que, Wayne Luk, Alexander D. Tapper, Duc Hoang, Noah Paladino, Philip C. Harris, Bo-Cheng Lai, Manuel Valentin, Ryan Forelli, Seda Ogrenci Memik, Lino Gerlach, Rian Brooks Flynn, Mia Liu, Daniel Diaz 0003, Elham E Khoda, Melissa Quinnan, Russell Solares, Santosh Parajuli, Mark S. Neubauer, Christian Herwig, Ho Fung Tsoi, Dylan S. Rankin, Shih-Chieh Hsu, Scott Hauck |
ACM Trans. Reconfigurable Technol. Syst. | 48 |
| 2025 | HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEPabstractCharged particle trajectory reconstruction is a critical task in high-energy physics (HEP), particularly for collision analysis in the Large Hadron Collider (LHC). In the LHC, the Level-1 Trigger (L1T) system must perform trajectory reconstruction with ultralow latency and very high throughput. Graph Neural Networks (GNNs)-based trajectory reconstruction on FPGAs has shown promising performance. However, the existing FPGA-based implementations are incomplete, supporting only the GNN processing stage and lacking the graph construction and track building parts of the task flow. Yun-Chen Yang, Hsuan-Wei Yu, Bo-Cheng Lai, Shih-Chieh Hsu, Mark S. Neubauer, Santosh Parajuli |
FPGA | 5 |
| 2025 | From Signals to Features to Insights: Multi-Level Novelty Detection for Fast Scientific DiscoveryabstractMost scientific discoveries depend on identifying novel signals hidden in massive, noisy datasets generated by modern experiments. Traditional novelty detection methods are often insufficient in speed, robustness, and adaptability to resource-constrained environments. We discuss a perspective on a hierarchical framework for multi-level novelty detection spanning sensor signals, feature representations, and model outputs. At the signal level, we discuss analog circuits that extract statistical densities and moments in real-time, enabling interpretable and energy-efficient filtering. At the feature level, we introduce Likelihood Regret, an unsupervised measure that detects anomalies by retraining generative models on shared latent representations, with optimizations for embedded deployment. At the output level, we leverage predictive uncertainty, applying both compute-efficient Monte Carlo reuse and Monte Carlo-free techniques like evidential learning and conformal inference. Our framework demonstrates how integrating novelty detection across the sensing-to-inference can accelerate insights in domains such as high-energy physics. Devashri Naik, Nastaran Darabi, Sina Tayebati, Dinithi Jayasuriya, Shamma Nasrin, Danush Shekar, Corrinne Mills, Benjamin Parpillon, Farah Fahim, Mark S. Neubauer, Amit Ranjan Trivedi |
VTS | 10 |
| 2023 | Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAsabstractIn-time particle trajectory reconstruction in the Large Hadron Collider is challenging due to the high collision rate and numerous particle hits. Using GNN (Graph Neural Network) on FPGA has enabled superior accuracy with flexible trajectory classification. However, existing GNN architectures have inefficient resource usage and insufficient parallelism for edge classification. This paper introduces a resource-efficient GNN architecture on FPGAs for low latency particle tracking. The modular architecture facilitates design scalability to support large graphs. Leveraging the geometric properties of hit detectors further reduces graph complexity and resource usage. Our results on Xilinx UltraScale+ VU9P demonstrate 1625x and 1574x performance improvement over CPU and GPU respectively. Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer |
FPL | 9 |