This paper presents how we leverage AI-human collaboration to develop an end-to-end, automated design flow for digitally controlled oscillators (DCOs), a key radio-frequency (RF) integrated circuits (ICs) building block that dominates phase noise and jitter performance of RF systems. Specifically, we decompose the DCO design process into two steps and use AI to enhance productivity and optimize performance within each step. Additionally, we demonstrate how AI can assist RF IC designers in creating unconventional circuit components to tackle challenging design specifications. Overall, the proposed flow is capable of synthesizing the DCO design including the schematic and layout in 80 seconds after one-time training, and is frequency agile between 1 and 20 GHz. Moreover, it can select the most robust design under process variations when multiple design parameters meet target specifications under the nominal condition. The proposed automated DCO design flow is demonstrated using two silicon prototypes implemented in the GlobalFoundries $22-\mathrm{nm}$ CMOS SOI process. In the measurements, they achieve $\gt 192.4-\mathrm{dBc} / \mathrm{Hz}$ figure-of-merit (FoM) and $\lt 1.5-\mathrm{kHz}$ frequency resolution at 7.1 to 8.6 GHz and 3.8 to 4.6 GHz, outperforming existing manual designs at similar frequencies.

The front-end synthesis of analog circuits has been a long-standing challenge since the advent of integrated circuits. Many methods, ranging from conventional optimization-based techniques to emerging learning-based approaches, have been extensively explored to address this challenge. Yet, these methods are data-driven and often suffer from low design efficiency, due to their heavy reliance on time-consuming circuit simulators, which are frequently used in the synthesis loop for real-time evaluation of the evolving circuit design. In addition, benchmarking these methods is also largely unachievable due to their exclusive use of commercial semiconductor technology for evaluation. This “Late Breaking Results” introduces Opera, an open and efficient platform for the data-driven synthesis of analog circuits. Specifically, Opera develops efficient surrogate models for various circuits and integrates them into open-source OpenAI Gym-like environments to enable efficient synthesis. Case studies on exemplary circuits show that this platform can accelerate the conventional data-driven synthesis flow by up to $40 \times$. It also enables the benchmarking of various synthesis methods with standardized environments built upon an open-source semiconductor process.

The exponential growth of information and computational workloads has created unprecedented demands for high-productivity development of computer hardware built on foundational semiconductor integrated circuits (ICs). Yet, the lack of effective design automation techniques makes developing analog ICs–indispensable in ubiquitous computer systems–a significant bottleneck for overall design productivity and cost efficiency across the IC ecosystem. Excitingly, recent advances in generative AI present transformative opportunities to tackle the complexity and large-scale challenges of modern analog/radio-frequency (RF) IC design. This work introduces a first-of-its-kind multi-agent generative synthesis framework for analog/RF circuits. Specifically, our approach formulates analog synthesis as a multi-stage generative AI problem: first generating a novel topology conditioned on high-level textual descriptions, and then producing high-quality device parameters to meet given design specifications for the generated circuit topology. This novel paradigm offers distinct advantages over traditional methods, including controllable novelty in topology generation and significantly improved inverse design efficiency. Beyond topology generation and inverse design, our method enables broader applications such as synthetic dataset generation and privacy-preserving data sharing–emerging challenges in data-driven electronic design automation (EDA) due to the computationally intensive and confidential nature of analog/RF circuit design. This work paves the way for next-generation generative AI-driven multi-agent synthesis in analog/RF EDA.

Organic thin-film transistor (OTFT) is a promising device technology for flexible large-area high-channel-count active-matrix neurostimulation system due to its flexibility and biocompatibility. However, circuits made by OTFT might be sensitive to device variation. As a result, it is difficult to achieve precise neurostimulation without any compensation structure in the pixel circuits. This work proposes a 6T2C threshold voltage compensation circuit for neurostimulation, which has low output current variation of 10.53%, reduced from the variation of 17.85% without compensation. We also improve the OTFT fabrication process with encapsulation to allow the circuits to operate under an electrolyte environment. Using the pixel circuits, we implement a 256-channel active-matrix neurostimulation system. The system can output stimulation with any pattern and allow each channel to output independently and simultaneously.

The observation surface of gravity data is often undulating, and the density inversion efficiency of gravity data is seriously reduced due to the low computational efficiency of the kernel function when the undulating surface is considered, which makes it impossible to apply to the detailed inversion of large-scale data. We proposed a multivariate geometric equivalent transformation (MGET) method to rapidly compute the kernel matrix with an undulating observation surface for improving density inversion efficiency. We first build the equivalence relation of the kernel function for different grid nodes, grid cells, and adjacent layers with a structured hexahedron mesh, which reduces the computation time and the number of kernel function, and can significantly improve the density inversion efficiency of gravity data. Tests show that the kernel matrices computed by the MGET method are accurate and efficient, and the computational efficiency of the kernel function is improved by more than ten times, and the density inversion can be performed efficiently and quickly. Finally, we apply the MGET method to real gravity data from Harbin City, China, to obtain the fault distribution and trends. This will contribute to future city construction planning.

Large DNNs with mixed-precision quantization can achieve ultra-high compression while retaining high classification performance. However, because of the challenges in finding an accurate metric that can guide the optimization process, these methods either sacrifice significant performance compared to the 32-bit floating-point (FP-32) baseline or rely on a compute-expensive, iterative training policy that requires the availability of a pre-trained baseline. To address this issue, this paper presents BMPQ, a training method that uses bit gradients to analyze layer sensitivities and yield mixed-precision quantized models. BMPQ requires a single training iteration but does not need a pre-trained baseline. It uses an integer linear program (ILP) to dynamically adjust the precision of layers during training, subject to a fixed hardware budget. To evaluate the efficacy of BMPQ, we conduct extensive experiments with VGG16 and ResNet18 on CIFAR-10, CIFAR-100, and Tiny-ImageNet datasets. Compared to the baseline FP-32 models, BMPQ can yield models that have 15.4x fewer parameter bits with negligible drop in accuracy. Compared to the SOTA “during training”, mixed-precision training scheme, our models are 2.1 x, 2.2x, and 2.9x smaller, on CIFAR-10, CIFAR-100, and Tiny-ImageNet, respectively, with an improved accuracy of up to 14.54%.