This paper presents a high-bandwidth memory (HBM) PHY interface employing a reconfigurable differentiator-based crosstalk cancellation (XTC) scheme to mitigate coupling noise arising in high-density silicon interposer channels. By introducing a novel analysis of RC-dominant channels from the perspective of group delay, the proposed XTC achieves precise delay matching by optimal differentiator parameter selection, without requiring additional hardware. Furthermore, the self-loading induced by multiple-aggressor XTC is compensated by reconfiguring the XTC scheme into a bandwidth extension scheme in which the bi-directional signaling nature of HBM interface is leveraged. Additionally, the merged adder with multiple-XTC and decision-feedback equalization (DFE) is proposed to provide improved offset and power performance. Fabricated in a 28-nm CMOS process, the prototype transceiver achieves an edge density of 15 Tb/s/mm and energy efficiency of 0.53 pJ/bit with high-density on-chip channels of 7.5-dB Nyquist loss. The proposed XTC technique reduces the crosstalk-induced jitter (CIJ) by four aggressors by 72.4% at a signal-to-crosstalk ratio of 0.45 dB, achieving an eye-opening of 0.42 UI at a$10^{-12}$bit error rate (BER).

This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transceiver for next-generation high bandwidth memory (HBM) interfaces. Since HBM interfaces have over 1024 DQs, the interfaces need to improve energy efficiency and minimize area. The proposed PAM-4 transmitter employs capacitive drivers to extend bandwidth with low power and uses accumulation-mode NFET capacitors as AC coupling capacitors to reduce area. A high-level boosting technique (HLB) is introduced to compensate for the capacitance variation according to output voltage levels, thereby improving the ratio of level mismatch (RLM). A feed-forward equalization (FFE)-combined capacitive PAM-4 driver effectively removes inter-symbol interference (ISI), leading to higher data rates. To define the DC level without using dissipated static power, a ground-forcing technique is applied. The silicon interposer channel was emulated using a 5.9 mm on-chip wire. A prototype chip was fabricated in a 28 nm CMOS process and occupied 0.0039 mm2. The prototype achieves data rates of 16 Gb/s with an energy efficiency of 67.2 fJ/b/mm and RLM of 0.992.

This paper presents a single-ended, 4-level pulse amplitude modulation (PAM-4) receiver (RX) designed for maximum transition avoidance (MTA)-coded signaling. The RX employs a decision feedback power saving (DFPS) scheme and a 1-tap partial decision feedback equalizer (pDFE) for low-power memory interfaces. MTA-coded signaling eliminates maximum transitions. Utilizing this property, the proposed DFPS scheme reduces comparator power consumption by deactivating some comparators based on the previous pattern. Furthermore, the proposed pDFE, in a hardware- and power-efficient manner, selectively equalizes only the middle transitions, which creates the worst-case eye-opening due to switching jitter and inter-symbol interference (ISI) in MTA-coded signaling, resulting in an improved overall eye-opening. Simulation results show that the proposed scheme improves the timing margin from 0.43UI to 0.46UI for the LSB and from 0.47UI to 0.51UI for the MSB while achieving an 8.9% reduction in comparator power consumption.

This paper presents a single-ended hybrid digital-to-analog converter (DAC)-based transmitter (TX) using four-level pulse-amplitude modulation (PAM-4) for memory interfaces. The proposed hybrid DAC composed of voltage mode (VM) driver unit segments and current mode (CM) driver unit segments reduces the total number of unit segments without increasing complexity in impedance matching. Therefore, the hybrid DAC significantly reduces area and the associated power consumption. Digital signal processing (DSP)-based feed-forward equalization (FFE) provides precise and flexible equalization. The proposed linearity enhancement technique compensates for additional non-linearity caused by short-length devices in the CM driver segments. The proposed TX operating at 40Gb/s/pin consumes 30.9mW with 1.0/0.9/0.15V supply voltages, achieving 0.77pJ/bit energy efficiency and a level separation mismatch ratio (RLM) of 0.989. The TX occupies an active area of 0.023mm2.

The dual-rank configuration is one of the parallelization methods to increase the memory capacity for mobile applications. However, the stub mainly composed of the redistribution layer causes resonance reflections and its reflection interval reaches the bit period, which distorts signal and limits the signal bandwidth. A single-ended duobinary transmitter that utilizes the reflection is presented for dual-rank mobile memory interfaces where reflections dominate. The reflection is included in the transfer function for duobinary modulation, which allows the transmitter to have a wide eye opening and high energy efficiency. Two-tap reverse feed-forward equalization and slew-rate control are used to support the duobinary modulation in combination with the reflection. A prototype chip fabricated in a 65 nm CMOS process has an area of 0.0378 mm2and consumes 1.24 pJ/bit. It is verified at data rates of 8, 9 and 10 Gb/s/pin where the flight time of the 9 mm stub is 55.6 ps.

The increasing data rate of serial links makes it difficult to match timing constraints of serializers in transmitters. Delay compensation clock buffers can alleviate this issue by matching the timing between data and clock. However, these buffers consume significant power and become sources of noise to the transmitter output. The problem is more serious for serializers other than 2n:1, and using only 2n:1 serializer could be a limitation on system design. In this paper, a 20:1 serializer using two calibration feedback loops is presented to solve this issue and reduce power consumption. The two loops detect the phase difference between data and clock, and automatically align the clock phase to the center of the data phase. The loops eliminate the power-consuming clock buffers on the critical clock path and operate at maximum quarter rate, enabling the transmitter to have low power consumption and high performance. A 6.4 Gb/s serializer prototype is fabricated in 55-nm CMOS process with a 1.2 V supply voltage. It achieves 97.5 ps eye width, which is 62.4% of a unit interval (UI) using PRBS-7 data, and its energy efficiency is 1.60 pJ/bit.

In this paper, we propose a dynamic comparator that improved the operation performance of receiver (RX) with the effort to reduce power consumption. It is implemented via double-tail StrongARM latch comparator with an active inductor and efforts are made to minimize power consumption for high-speed resulting in better energy efficiency at the targeted high frequency. In this regard, our comparator is suitable for memory application RX to satisfy both low-power and high-speed. It is applied to the single-ended RX designed with a continuous-time linear equalizer, a clock generator and a quarter-rate 2-tap decision-feedback equalizer which is appropriate for the high-frequency memory application. Compared to the conventional one, our design, fabricated in 55nm CMOS process, provides an improvement of 7% in unit interval (UI) margin under the same power consumption and receives up to 10Gb/s PRBS15 data at BER < 10-12 with 0.4 UI margin and energy efficiency of 0.67pJ/bit.