ZuSE-KI-Mobil (ZuKIMo) is a nationally funded research project, currently in its intermediate stage. The goal of the ZuKIMo project is to develop a new System-on-Chip (SoC) platform and corresponding ecosystem to enable efficient Artificial Intelligence (AI) applications with specific requirements. With ZuKIMo, we specifically target applications from the mobility domain, i.e. autonomous vehicles and drones. The initial ecosystem is built by a consortium consisting of seven partners from German academia and industry. We develop the SoC platform and its ecosystem around a novel AI accelerator design. The customizable accelerator is conceived from scratch to fulfill the functional and non-functional requirements derived from the ambitious use cases. A tape-out in 22 nm FDX-technology is planned in 2023. Apart from the System-on-Chip hardware design itself, the ZuKIMo ecosystem has the objective of providing software tooling for easy deployment of new use cases and hardware-CNN co-design. Furthermore, AI accelerators in safety-critical applications like our mobility use cases, necessitate the fulfillment of safety requirements. Therefore, we investigate new design methodologies for fault analysis of Deep Neural Networks (DNNs) and introduce our new redundancy mechanism for AI accelerators.

Embedded systems usually integrate multiple Pro-cessing Elements (PEs) on a single chip. Various PEs are con-nected to the same Tightly Coupled Memory (TCM) to increase the area and energy efficiency. However, memory sharing comes at the cost of conflicts resulting in performance degradation. To counteract this issue, Access Interval Prediction (AIP) has been introduced in the literature to predict the interval between two memory accesses. State-of-the-art AIP units are based on predictors proposed for branch prediction, such as TAgged GEometric (TAGE). This work shows for the first time that several types of neural networks are suitable for AIP as well. By treating AIP as a classification problem, we can continue to decrease the error rate compared to the TAGE predictor. For example, Vision Transformer (ViT) networks reduce the average error rate by over one-third to 2.1 percent. Through our investigation, we demonstrate that offline training alone is sufficient since the memory access traces contain the same repetitive patterns independent from the input parameters of the program run.

The prototyping of embedded platforms demands rapid exploration of multi-dimensional parameter sets. Especially the design of the memory system is essential to guarantee high utilization while reducing conflicts at the same time. To aid the design process, several probabilistic models to estimate the throughput of interleaved memory systems have been proposed. While accurately estimating the average throughput of the system, these models fail to determine the impact on individual processing elements. To mitigate this divergence, we extend three known models to include non-uniform access probabilities and priorities.

With the advent of the fourth industrial revolution i.e. Industry 4.0, plants and factories are becoming smarter and interconnected. The transitions demand vertical integration and seamless connectivity. For this purpose, there is a need for semantic communication between various devices including the heavily resource-constrained field devices. To address this, a real-time capable hardware-based implementation of a well-established semantic communication protocol, i.e. OPC Unified Architecture was designed and developed. This chip-based implementation is power-efficient and compact, making it suitable for the field level. The chip was analyzed and incorporated in a demonstrator as a proof of concept of its integration at field level in a plant module of the process industry. Various opportunities are also examined where the chip could be utilized to deliver benefits to existing and future technologies.

Sharing tightly coupled memory in a multiprocessor system-on-chip is a promising approach to improve the programming flexibility as well as to ease the constraints imposed by area and power. However, it poses a challenge in terms of access latency. In this paper, we present a queue based memory management unit which combines the low latency access of shared tightly coupled memory with the flexibility of a traditional memory management unit. Our passive conflict detection approach significantly reduces the critical path compared to previously proposed methods while preserving the flexibility associated with dynamic memory allocation and heterogeneous data widths.

General frequency division multiplexing (GFDM) provides a proven approach for a flexible physical layer implementation in wireless communication systems. However, this flexibility requires additional processing steps within the critical system path, the hybrid automatic repeat request. This is especially critical for devices of the Internet of Things, which have a very small power footprint. To tackle this problem, we present a data mapping that allows efficient parallel computation of the GFDM algorithm by a standard Harvard CPU architecture. To utilize the new mapping, we derive semi-custom processor configurations based on fixed-point arithmetic, which achieve a throughput close to the theoretical bound. In comparison with a custom FPGA implementation, we deliver 9 percent of the throughput, while only consuming 0.1 percent of the power. Thus, we achieve 14 times higher energy efficiency.

5G is not one problem and one solution, but spans a breadth of applications with largely differing requirements. One solution for all seems therefore inadequate. We therefore present a modular signal processor MPSoC architecture which can be tiled into the size to address the requirement as needed. We name it “Kachel”, the German word for “tile”.

Sharing scratchpad memory improves memory utilization but incurs conflicts. Existing statistical models for throughput estimation of shared memory systems assume mainly online memory arbitration, i.e., the memory access and arbitration logic are integrated into a single path. However, these models are not suited for modeling memory systems deploying off-line arbitration as they do not reflect the additional latency of such arbiters. To cope with this problem, we extend the existing occupancy and Markov models by including appropriate weighing parameters. We show that our extension can reduce the error of the original model by 71 percent over a wide range of parameters.