Computation-in-Memory (CiM) is a promising solution to reduce the energy and latency caused by frequent data transfers between the processor and memory, a problem commonly referred to as the memory wall. For instance, comparing binary patterns to measure similarity is a common and challenging task in today’s emerging artificial intelligence applications. This can be implemented efficiently using Content Addressable Memory (CAM), which is well-suited for CiM-based acceleration of such tasks. To improve energy efficiency and performance, non-volatile memories (NVM) such as ReRAM (Redox-based RAM) can be utilized for the realization of CiMbased CAM. However, ReRAM is highly susceptible to process variations (PV), due to the immaturity of its process and inherent stochasticity. Moreover, the analog realization of CAM functionality using NVMs makes it more sensitive to these non-idealities. Conventional March tests, originally designed for memory fault detection, become ineffective in the presence of PV, which can alter ReCAM behavior and lead to test escapes. To address these challenges, this work systematically analyzes the impact of PV on ReCAM functionality. It proposes a generalized PV-aware March test that optimizes test patterns for both hard and PV-induced soft defects, achieving 100% defect coverage.

Content Addressable Memory enables high-speed binary pattern matching and is widely used in various applications. Exploiting Resistive Random Access Memory (ReRAM) for CAM (ReCAM) realization offers advantages in terms of non-volatility, high density, and low power consumption using the Computation in Memory (CiM) concept. However, the unique defects of ReRAM combined with CMOS fabrication defects, introduce new faulty behaviors that complicate detection and diagnosis, thereby increasing the risk of test escapes and field failures. However, diagnosing faulty cells in ReCAM is crucial for analyzing failure mode, which helps improve manufacturing yield. It also promotes defect and fault tolerance both post-manufacturing and during runtime. Pinpointing faulty cells within the ReCAM array is particularly challenging, especially when all cells are connected to the same match-line (ML). Diagnosis also plays a critical role at runtime by enabling fault tolerance through mechanisms such as bypassing defective cells. This paper proposes a novel Design-for-Testability (DfT) approach for ReCAM diagnosis that utilizes infinitesimal voltage differences to identify the location of faulty cells. The proposed DfT circuitry and the accompanied diagnosis flow enhance diagnostic precision by enabling adjustable gain and sampling time in a multi-step process, effectively identifying faulty cells within the array. The simulation results of two distinct fault scenarios, applied to the binary patterns of all-match and all-mismatch conditions, demonstrate the effectiveness of the proposed DfT technique in achieving fine-grained fault detection across the ReCAM array. Furthermore, using this approach reduces the time complexity by more than half compared to the March-based approach with negligible overhead in area and power.

Measuring similarity between binary patterns is a key kernel in various data-intensive applications such as search engines and artificial intelligence (AI). However, due to the memory wall problem caused by frequent data transfers between processor cores and memory subsystems, executing these operations leads to high energy consumption and increased latency. One approach to mitigating this problem is to utilize Computing-in-Memory (CiM) architectures for the realization of Content-Addressable Memory (CAM) in such applications. Integrating Non-Volatile Memory (NVM) technologies can improve performance and energy efficiency. Redox-based Resistive Access Memory (ReRAM) is a promising candidate for implementation within NVM-based Content-Addressable Memory (CAM) due to its non-volatile nature, low power consumption, and highly distinct resistive levels. However, integrating NVM with conventional CMOS introduces unique fabrication challenges and failure mechanisms that are not seen in CMOS processes alone. Furthermore, the analog nature of CiM increases sensitivity to non-idealities in both ReRAM and CMOS, resulting in new fault behaviors that affect the quality of ReRAM-based CAM (ReCAM) blocks. Therefore, to ensure the high quality of the ReCAM functionality, this paper develops a March-like test algorithm tailored for the ReCAM array. The proposed March-like test algorithm is extendable and can achieve 100% fault coverage.

The computation-in-memory (CiM) paradigm is widely acknowledged to tackle the memory wall problem. Additionally, leveraging non-volatile resistive memory (NVM) technologies enhances the energy efficiency of the CiM by enabling analog computation. However, the reliability of the NVM-CiM is challenged due to the inherent device and circuit imperfections, the technology-level process variation, the sensing offset, and the analog nature of the computation. In this paper, we perform comprehensive reliability analysis and mitigation from the technology all the way to the CiM application. For this aim, we accurately model the NVM device variability and imperfection and effectively model the consequent errors at the circuit level by considering crossbar parasitic and sensing offset. Subsequently, we inject these modeled faults into the CiM-enabled full-system architecture. The study quantitatively assesses the masking capability of CiM applications and explores potential mitigation techniques to enhance the overall reliability of NVM-CiM.